XC3S50A-4FTG256C Datasheet, PDF (59/132 Pages) Xilinx, Inc – Architectural and Configuration Overview

DC and Switching Characteristics
Serial Peripheral Interface (SPI) Configuration Timing
PROG_B
(Input)
PUDC_B
(Input)
VS[2:0]
(Input)
M[2:0]
(Input)
INIT_B
(Open-Drain)
CCLK
DIN
(Input)
CSO_B
MOSI
PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process.
<1:1:1>
T_MINIT
<0:0:1>
T_INITM
T_CCLK1
Mode input pins M[2:0] and variant select input pins VS[2:0] are sampled when INIT_B
goes High. After this point, input values do not matter until DONE goes High, at which
point these pins become user-I/O pins.
T_MCCL1 T_MCCH1
New ConfigRate active
T_MCCLn
T_CCLK1
T_CCLKn
T_MCCHn
T_V
T_CSS
Data
Data
T_DCC
Data
Data
T_CCD
T_CCO
Command
(msb)
Command
(msb-1)
T_DSU
T_DH
Pin initially pulled High by internal pull-up resistor if PUDC_B input is Low.
Pin initially high-impedance (Hi-Z) if PUDC_B input is High. External pull-up resistor required on CSO_B.
Shaded values indicate specifications on attached SPI Flash PROM.
Figure 14: Waveforms for Serial Peripheral Interface (SPI) Configuration
DS529-3_06_102506
Table 52: Timing for Serial Peripheral Interface (SPI) Configuration Mode
Symbol
Description
T_CCLK1
T_CCLKn
T_MINIT
Initial CCLK clock period
CCLK clock period after FPGA loads ConfigRate bitstream option setting
Setup time on VS[2:0] variant-select pins and M[2:0] mode pins before the
rising edge of INIT_B
T_INITM
Hold time on VS[2:0] variant-select pins and M[2:0] mode pins after the
rising edge of INIT_B
T_CCO
T_DCC
T_CCD
MOSI output valid delay after CCLK falling clock edge
Setup time on the DIN data input before CCLK rising clock edge
Hold time on the DIN data input after CCLK rising clock edge
Minimum
50
Maximum
See Table 46
See Table 46
–
0
–
See Table 50
See Table 50
See Table 50
Units
ns
ns
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
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