XC3S50A-4FTG256C Datasheet, PDF (43/132 Pages) Xilinx, Inc – Architectural and Configuration Overview

DC and Switching Characteristics
Table 31: CLB Distributed RAM Switching Characteristics
Symbol
Description
Clock-to-Output Times
T_SHCKO
Time from the active edge at the CLK input to data appearing on
the distributed RAM output
Setup Times
T_DS
Setup time of data at the BX or BY input before the active
transition at the CLK input of the distributed RAM
T_AS
Setup time of the F/G address inputs before the active transition
at the CLK input of the distributed RAM
T_WS
Setup time of the write enable input before the active transition at
the CLK input of the distributed RAM
Hold Times
T_DH
Hold time of the BX and BY data inputs after the active transition
at the CLK input of the distributed RAM
T_AH, T_WH
Hold time of the F/G address inputs or the write enable input after
the active transition at the CLK input of the distributed RAM
Clock Pulse Width
T_WPH, T_WPL Minimum High or Low pulse width at CLK input
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8.
Table 32: CLB Shift Register Switching Characteristics
Symbol
Description
Clock-to-Output Times
T_REG
Time from the active edge at the CLK input to data appearing on
the shift register output
Setup Times
T_SRLDS
Setup time of data at the BX or BY input before the active
transition at the CLK input of the shift register
Hold Times
T_SRLDH
Hold time of the BX or BY data input after the active transition at
the CLK input of the shift register
Clock Pulse Width
T_WPH, T_WPL Minimum High or Low pulse width at CLK input
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8.
-5
Min
Max
–
1.69
–0.07
–
0.18
–
0.30
–
0.13
–
0.01
–
0.88
–
-5
Min
Max
–
4.11
0.13
–
0.16
–
0.90
–
-4
Min Max
–
2.01
–0.02
–
0.36
–
0.59
–
0.13
–
0.01
–
1.01
–
-4
Min Max
–
4.82
0.18
–
0.16
–
1.01
–
Units
ns
ns
ns
ns
ns
ns
ns
Units
ns
ns
ns
ns
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
43