XC3S50A-4FTG256C Datasheet, PDF (62/132 Pages) Xilinx, Inc – Architectural and Configuration Overview

DC and Switching Characteristics
Table 55: Configuration Timing Requirements for Attached Parallel NOR BPI Flash
Symbol
Description
Requirement
Units
T_CE
(t_ELQV)
Parallel NOR Flash PROM chip-select time
T_CE ≤ T_INITADDR
ns
T_OE
(t_GLQV)
Parallel NOR Flash PROM output-enable time
T_OE ≤ T_INITADDR
ns
T_ACC
(t_AVQV)
Parallel NOR Flash PROM read access time
T_ACC ≤ 50%T_CCLKn(min) – T_CCO – T_DCC – PCB ^ns
T_BYTE
For x8/x16 PROMs only: BYTE# to output valid time⁽³⁾
(t_FLQV, t_FHQV)
T_BYTE ≤ T_INITADDR
ns
Notes:
1. These requirements are for successful FPGA configuration in BPI mode, where the FPGA generates the CCLK signal. The
post-configuration timing can be different to support the specific needs of the application loaded into the FPGA.
2. Subtract additional printed circuit board routing delay as required by the application.
3. The initial BYTE# timing can be extended using an external, appropriately sized pull-down resistor on the FPGA’s LDC2 pin. The resistor
value also depends on whether the FPGA’s PUDC_B pin is High or Low.
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DS529-3 (v2.0) August 19, 2010