XC3S50A-4FTG256C Datasheet, PDF(92/132 Page) Xilinx, Inc – Architectural and Configuration Overview

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XC3S50A-4FTG256C Datasheet, PDF (92/132 Pages) Xilinx, Inc – Architectural and Configuration Overview

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Pinout Descriptions

FT256 Footprint (XC3S200A, XC3S400A)

A GND

B TDI

PROG_B

I/O

L19P_0

I/O

L18P_0

I/O

L17P_0

I/O

L15P_0

TMS

I/O

I/O VCCO_0 I/O

L19N_0 L18N_0

L15N_0

I/O

L13P_0

Bank 0

I/O

L12P_0

GCLK10

I/O

L10N_0

GCLK7

I/O

L08N_0

GND

I/O

L12N_0

GCLK11

VCCO_0

I/O

L08P_0

11 12 13 14

I/O

L07N_0 L05N_0 L04N_0 L04P_0

TCK

GND

I/O

L05P_0

VCCO_0

I/O

L02N_0

I/O

L02P_0

VREF_0

GND

TDO

I/O

L01N_3

I/O

L01P_3

GND

I/O

L20P_0

VREF_0

I/O

L17N_0

I/O

L16N_0

I/O

L13N_0

I/O

L11P_0

GCLK8

I/O

L10P_0

GCLK6

I/O

L09P_0

GCLK4

I/O

L07P_0

I/O

L03P_0

I/O

L01N_0

GND

I/O

L24N_1

A25

I/O

L24P_1

A24

I/O

L03P_3

VCCO_3

I/O

L02N_3

I/O

L02P_3

I/O

L20N_0

PUDC_B

INPUT

I/O

L16P_0

I/O

L11N_0

GCLK9

I/O

L09N_0

GCLK5

I/O

L06P_0

I/O

L03N_0

INPUT

I/O

L01P_0

I/O

L23N_1

A23

I/O

L22N_1

A21

I/O

L22P_1

A20

I/O

L03N_3

I/O

L05N_3

I/O

L05P_3

INPUT

L04P_3

GND

INPUT

I/O

L14N_0 VCCO_0

VREF_0

INPUT

VREF_0

I/O

L06N_0 VCCAUX

VREF_0

GND

I/O

L23P_1

A22

I/O

L20P_1

A18

VCCO_1

I/O

L18P_1

A14

I/O

L08P_3

GND

I/O

L07P_3

INPUT

L04N_3 VCCAUX

VREF_3

GND

INPUT

I/O

L14P_0

INPUT

L25N_1

INPUT

L25P_1

VREF_1

I/O

L20N_1

A19

I/O

L19N_1

A17

I/O

L18N_1

A15

I/O

L16N_1

A11

I/O

G L08N_3 L11P_3

VREF_3 LHCLK0

I/O

L09P_3

I/O

L07N_3

INPUT

L06N_3

VREF_3

INPUT VCCINT

L06P_3

GND

VCCINT

GND

INPUT

L21N_1

INPUT

L21P_1

VREF_1

I/O

L19P_1

A16

I/O

L17N_1

A13

GND

I/O

L16P_1

A10

I/O

H L11N_3 VCCO_3 L12P_3

LHCLK1

LHCLK2

I/O

L14N_3

L14P_3

L12N_3

IRDY2

LHCLK5 LHCLK4 LHCLK3

I/O

K L15N_3

LHCLK7

GND

I/O

L15P_3

TRDY2

LHCLK6

I/O

L09N_3

I/O

L17P_3

I/O

L18P_3

I/O

L10N_3

VCCO_3

INPUT

L21P_3

I/O

L10P_3

I/O

L17N_3

INPUT

L21N_3

INPUT VCCINT GND INPUT INPUT

L13P_3

L13P_1 L13N_1

INPUT

L13N_3

GND

INPUT

VCCINT L09P_1

VREF_1

INPUT

L09N_1

GND VCCINT GND VCCINT INPUT

L04P_1

VCCO_1

I/O

L10P_1

INPUT

L04N_1

VREF_1

I/O

L17P_1

A12

I/O

L10N_1

I/O

L06N_1

I/O

L14N_1

RHCLK5

I/O

L14P_1

RHCLK4

I/O

L15P_1

IRDY1

RHCLK6

VCCO_1

I/O

L15N_1

RHCLK7

I/O

L12N_1

TRDY1

RHCLK3

I/O

L11N_1 L11P_1 L12P_1

RHCLK1 RHCLK0 RHCLK2

I/O

L L16P_3

VREF_3

I/O

L16N_3

I/O

L18N_3

I/O

L19N_3

INPUT

L25P_3

INPUT

L25N_3 INPUT

VREF_3

INPUT

INPUT INPUT

VREF_2 VREF_2

GND

I/O

VCCAUX L06P_1

I/O

L08P_1

GND

I/O

L08N_1

I/O

L20P_3

VCCO_3

I/O

L19P_3

I/O

L24N_3

GND VCCAUX INPUT INPUT VCCO_2 I/O INPUT

VREF_2 VREF_2

L13N_2 VREF_2

GND

I/O

L05P_1

I/O

L05N_1

VREF_1

I/O

L07P_1

I/O

L07N_1

I/O

L20N_3

I/O

L22N_3

I/O

L23P_3

T GND

I/O

L22P_3

I/O

L24P_3

I/O

L01P_2

INPUT

VREF_2

I/O

L23N_3

GND

I/O

L01N_2

I/O

L04N_2

VS0

I/O

L02P_2

I/O

L03P_2 VCCO_2

RDWR_B

I/O

L05N_2

I/O

L02N_2

CSO_B

I/O

L03N_2

VS2

I/O

L05P_2

I/O

L06P_2

I/O

L04P_2

VS1

I/O

L07N_2

GND

I/O

L06N_2

I/O

L07P_2

I/O

L08N_2

I/O

L08P_2

I/O

L10P_2

GCLK14

I/O

L09P_2 VCCO_2

GCLK12

I/O

L09N_2 L10N_2

GCLK13 GCLK15

I/O

L11P_2

GCLK0

I/O

L11N_2

GCLK1

I/O

L12P_2

GCLK2

I/O

L12N_2

GCLK3

I/O

L13P_2

I/O

L14N_2

MOSI

CSI_B

GND

I/O

L14P_2

I/O

L16N_2 L19P_2

I/O

L16P_2

I/O

L17N_2

I/O

L15N_2

DOUT

VCCO_2

I/O

L15P_2

AWAKE

I/O

L17P_2

INIT_B

I/O

L01P_1

HDC

I/O

L01N_1

LDC2

VCCO_1

I/O

L03N_1

I/O

L19N_2

GND

I/O

L02N_1

LDC0

I/O

L03P_1

I/O

L18N_2

I/O

L20N_2

CCLK

I/O

L02P_1

LDC1

I/O

L18P_2

I/O

L20P_2

DIN/MISO

DONE

SUSPEND

GND

Bank 2

Figure 21: XC3S200A and XC3S400A FT256 Package Footprint (Top View)

DS529-4_06_012009

I/O: Unrestricted,

general-purpose user I/O

DUAL: Configuration pins,

then possible user I/O

VREF: User I/O or input

voltage reference for bank

INPUT: Unrestricted,

general-purpose input pin

CLK: User I/O, input, or

global buffer input

VCCO: Output voltage

supply for bank

SUSPEND: Dedicated

SUSPEND and

dual-purpose AWAKE

Power Management pins

CONFIG: Dedicated

configuration pins

JTAG: Dedicated JTAG

port pins

VCCINT: Internal core

supply voltage (+1.2V)

0 N.C.: Not connected

28 GND: Ground

VCCAUX: Auxiliary supply

voltage

www.xilinx.com

DS529-4 (v2.0) August 19, 2010

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