XC3S50A-4FTG256C Datasheet, PDF (106/132 Pages) Xilinx, Inc – Architectural and Configuration Overview

Pinout Descriptions
Table 81: Spartan-3A FG400 Pinout(Continued)
Bank
Pin Name
FG400
Ball
Type
VCCAUX TDO
E17
JTAG
VCCAUX TMS
E4
JTAG
VCCAUX VCCAUX
A13 VCCAUX
VCCAUX VCCAUX
E16 VCCAUX
VCCAUX VCCAUX
H1 VCCAUX
VCCAUX VCCAUX
K13 VCCAUX
VCCAUX VCCAUX
L8 VCCAUX
VCCAUX VCCAUX
N20 VCCAUX
VCCAUX VCCAUX
T5 VCCAUX
VCCAUX VCCAUX
Y8 VCCAUX
VCCINT VCCINT
J10 VCCINT
VCCINT VCCINT
J12 VCCINT
VCCINT VCCINT
K9
VCCINT
VCCINT VCCINT
K11 VCCINT
VCCINT VCCINT
L10 VCCINT
VCCINT VCCINT
L12 VCCINT
VCCINT VCCINT
M9 VCCINT
VCCINT VCCINT
M11 VCCINT
VCCINT VCCINT
N10 VCCINT
User I/Os by Bank
Table 82 indicates how the 311 available user-I/O pins are
distributed between the four I/O banks on the FG400
package. The AWAKE pin is counted as a dual-purpose I/O.
Table 82: User I/Os Per Bank for the XC3S400A and XC3S700A in the FG400 Package
Package
Edge
I/O Bank Maximum I/O
I/O
All Possible I/O Pins by Type
INPUT
DUAL
VREF
Top
0
77
50
12
1
6
Right
1
79
21
12
30
8
Bottom
2
76
35
6
21
6
Left
3
79
49
16
0
6
TOTAL
311
155
46
52
26
Footprint Migration Differences
The XC3S400A and XC3S700A FPGAs have identical
footprints in the FG400 package. Designs can migrate
between the XC3S400A and XC3S700A FPGAs without
further consideration.
CLK
8
8
8
8
32
106
www.xilinx.com
DS529-4 (v2.0) August 19, 2010