XC3S50A-4FTG256C Datasheet, PDF (60/132 Pages) Xilinx, Inc – Architectural and Configuration Overview

DC and Switching Characteristics
Table 53: Configuration Timing Requirements for Attached SPI Serial Flash
Symbol
T_CCS
Description
SPI serial Flash PROM chip-select time
Requirement
T_CCS ≤ T_MCCL1 – T_CCO
T_DSU
SPI serial Flash PROM data input setup time
T_DSU ≤ T_MCCL1 – T_CCO
T_DH
SPI serial Flash PROM data input hold time
T_DH ≤ T_MCCH1
T_V
SPI serial Flash PROM data clock-to-output time
T_V ≤ T_MCCLn – T_DCC
f_C or f_R
Maximum SPI serial Flash PROM clock frequency (also depends on
specific read command used)
f_C ≥
----------------¹----------------
T_CCLKn(min)
Notes:
1. These requirements are for successful FPGA configuration in SPI mode, where the FPGA generates the CCLK signal. The
post-configuration timing can be different to support the specific needs of the application loaded into the FPGA.
2. Subtract additional printed circuit board routing delay as required by the application.
Units
ns
ns
ns
ns
MHz
60
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DS529-3 (v2.0) August 19, 2010