XC3S50A-4FTG256C Datasheet, PDF (77/132 Pages) Xilinx, Inc – Architectural and Configuration Overview

Pinout Descriptions
User I/Os by Bank
Table 67 indicates how the 108 available user-I/O pins are
distributed between the four I/O banks on the TQ144
package. The AWAKE pin is counted as a dual-purpose I/O.
Table 67: User I/Os Per Bank for the XC3S50A in the TQ144 Package
Package
Edge
I/O Bank Maximum I/O
I/O
All Possible I/O Pins by Type
INPUT
DUAL
VREF
Top
0
27
14
1
1
3
Right
1
25
11
0
4
2
Bottom
2
30
2
0
21
1
Left
3
26
15
1
0
2
TOTAL
108
42
2
26
8
CLK
8
8
6
8
30
Footprint Migration Differences
The XC3S50A FPGA is the only Spartan-3A device offered
in the TQ144 package.
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
77