XC3S50A-4FTG256C Datasheet, PDF (101/132 Pages) Xilinx, Inc – Architectural and Configuration Overview

Pinout Descriptions
FG400: 400-ball Fine-pitch Ball Grid Array
The 400-ball fine-pitch ball grid array, FG400, supports two
different Spartan-3A FPGAs, the XC3S400A and the
XC3S700A. Both devices share a common footprint for this
package as shown in Table 81 and Figure 24.
Table 81 lists all the FG400 package pins. They are sorted
by bank number and then by pin name. Pairs of pins that
form a differential I/O pair appear together in the table. The
table also shows the pin number for each pin and the pin
type, as defined earlier.
An electronic version of this package pinout table and
footprint diagram is available for download from the Xilinx
website at
www.xilinx.com/support/documentation/data_sheets/
s3a_pin.zip.
Pinout Table
Table 81: Spartan-3A FG400 Pinout
Bank
Pin Name
FG400
Ball
0
IO_L01N_0
A18
0
IO_L01P_0
B18
0
IO_L02N_0
C17
0
IO_L02P_0/VREF_0
D17
0
IO_L03N_0
E15
0
IO_L03P_0
D16
0
IO_L04N_0
A17
0
IO_L04P_0/VREF_0
B17
0
IO_L05N_0
A16
0
IO_L05P_0
C16
0
IO_L06N_0
C15
0
IO_L06P_0
D15
0
IO_L07N_0
A14
0
IO_L07P_0
C14
0
IO_L08N_0
A15
0
IO_L08P_0
B15
0
IO_L09N_0
F13
0
IO_L09P_0
E13
0
IO_L10N_0/VREF_0
C13
0
IO_L10P_0
D14
0
IO_L11N_0
C12
0
IO_L11P_0
B13
0
IO_L12N_0
F12
0
IO_L12P_0
D12
0
IO_L13N_0
A12
Type
I/O
I/O
I/O
VREF
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
Table 81: Spartan-3A FG400 Pinout(Continued)
Bank
Pin Name
FG400
Ball
Type
0
IO_L13P_0
B12
I/O
0
IO_L14N_0
C11
I/O
0
IO_L14P_0
B11
I/O
0
IO_L15N_0/GCLK5
E11
GCLK
0
IO_L15P_0/GCLK4
D11
GCLK
0
IO_L16N_0/GCLK7
C10
GCLK
0
IO_L16P_0/GCLK6
A10
GCLK
0
IO_L17N_0/GCLK9
E10
GCLK
0
IO_L17P_0/GCLK8
D10
GCLK
0
IO_L18N_0/GCLK11
A8
GCLK
0
IO_L18P_0/GCLK10
A9
GCLK
0
IO_L19N_0
C9
I/O
0
IO_L19P_0
B9
I/O
0
IO_L20N_0
C8
I/O
0
IO_L20P_0
B8
I/O
0
IO_L21N_0
D8
I/O
0
IO_L21P_0
C7
I/O
0
IO_L22N_0/VREF_0
F9
VREF
0
IO_L22P_0
E9
I/O
0
IO_L23N_0
F8
I/O
0
IO_L23P_0
E8
I/O
0
IO_L24N_0
A7
I/O
0
IO_L24P_0
B7
I/O
0
IO_L25N_0
C6
I/O
0
IO_L25P_0
A6
I/O
0
IO_L26N_0
B5
I/O
0
IO_L26P_0
A5
I/O
0
IO_L27N_0
F7
I/O
0
IO_L27P_0
E7
I/O
0
IO_L28N_0
D6
I/O
0
IO_L28P_0
C5
I/O
0
IO_L29N_0
C4
I/O
0
IO_L29P_0
A4
I/O
0
IO_L30N_0
B3
I/O
0
IO_L30P_0
A3
I/O
0
IO_L31N_0
F6
I/O
0
IO_L31P_0
E6
I/O
0
IO_L32N_0/PUDC_B
B2
DUAL
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
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