XC3S50A-4FTG256C Datasheet, PDF (58/132 Pages) Xilinx, Inc – Architectural and Configuration Overview

DC and Switching Characteristics
Slave Parallel Mode Timing
PROG_B
(Input)
INIT_B
(Open-Drain)
CSI_B
(Input)
RDWR_B
(Input)
CCLK
(Input)
T_SMCCW
T_SMCSCC
T_SMDCC
T_SMCCD
T_SMCCCS
T_MCCH
T_SCCH
T_MCCL
T_SCCL
1/F_CCPAR
T_SMWCC
D0 - D7
(Inputs)
Notes:
Byte 0
Byte 1
Byte n
Byte n+1
DS529-3_02_051607
1. It is possible to abort configuration by pulling CSI_B Low in a given CCLK cycle, then switching RDWR_B Low or High in any subsequent
cycle for which CSI_B remains Low. The RDWR_B pin asynchronously controls the driver impedance of the D0 - D7 bus. When RDWR_B
switches High, be careful to avoid contention on the D0 - D7 bus.
2. To pause configuration, pause CCLK instead of de-asserting CSI_B. See UG332 Chapter 7 section “Non-Continuous SelectMAP Data
Loading” for more details.
Figure 13: Waveforms for Slave Parallel Configuration
Table 51: Timing for the Slave Parallel Configuration Mode
Symbol
Setup Times
T_SMDCC(2)
T_SMCSCC
T_SMCCW
Hold Times
T_SMCCD
T_SMCCCS
T_SMWCC
Clock Timing
T_CCH
T_CCL
F_CCPAR
Description
The time from the setup of data at the D0-D7 pins to the rising transition at the CCLK pin
Setup time on the CSI_B pin before the rising transition at the CCLK pin
Setup time on the RDWR_B pin before the rising transition at the CCLK pin
The time from the rising transition at the CCLK pin to the point when data is last held at
the D0-D7 pins
The time from the rising transition at the CCLK pin to the point when a logic level is last
held at the CSO_B pin
The time from the rising transition at the CCLK pin to the point when a logic level is last
held at the RDWR_B pin
The High pulse width at the CCLK input pin
The Low pulse width at the CCLK input pin
Frequency of the clock signal No bitstream compression
at the CCLK input pin
With bitstream compression
All Speed Grades
Min
Max
7
–
7
–
15
–
1.0
–
0
–
0
–
5
–
5
–
0
80
0
80
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8.
2. Some Xilinx documents refer to Parallel modes as “SelectMAP” modes.
Units
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
58
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DS529-3 (v2.0) August 19, 2010