XC3S50A-4FTG256C Datasheet, PDF (55/132 Pages) Xilinx, Inc – Architectural and Configuration Overview

DC and Switching Characteristics
Configuration Clock (CCLK) Characteristics
Table 46: Master Mode CCLK Output Period by ConfigRate Opti0on Setting
Symbol
Description
ConfigRate
Setting
Temperature
Range
T_CCLK1
CCLK clock period by
ConfigRate setting
1
(power-on value)
Commercial
Industrial
T_CCLK3
Commercial
3
Industrial
T_CCLK6
6 (default)
Commercial
Industrial
T_CCLK7
Commercial
7
Industrial
T_CCLK8
Commercial
8
Industrial
T_CCLK10
Commercial
10
Industrial
T_CCLK12
Commercial
12
Industrial
T_CCLK13
Commercial
13
Industrial
T_CCLK17
Commercial
17
Industrial
T_CCLK22
Commercial
22
Industrial
T_CCLK25
Commercial
25
Industrial
T_CCLK27
Commercial
27
Industrial
T_CCLK33
Commercial
33
Industrial
T_CCLK44
Commercial
44
Industrial
T_CCLK50
Commercial
50
Industrial
T_CCLK100
Commercial
100
Industrial
Notes:
1. Set the ConfigRate option value when generating a configuration bitstream.
Minimum
1,254
1,180
413
390
207
195
178
168
156
147
123
116
103
97
93
88
72
68
54
51
47
45
44
42
36
34
26
25
22
21
11.2
10.6
Maximum
2,500
833
417
357
313
250
208
192
147
114
100
93
76
57
50
25
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
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