|
XC3S50A-4FTG256C Datasheet, PDF (53/132 Pages) Xilinx, Inc – Architectural and Configuration Overview | |||
|
◁ |
DC and Switching Characteristics
Suspend Mode Timing
Entering Suspend Mode
SUSPEND Input
Exiting Suspend Mode
sw_gwe_cycle
sw_gts_cycle
AWAKE Output
Flip-Flops, Block RAM,
Distributed RAM
FPGA Outputs
FPGA Inputs,
Interconnect
tSUSPENDHIGH_AWAKE
tSUSPENDLOW_AWAKE
tSUSPEND_GWE
tAWAKE_GWE
Write Protected
tSUSPEND_GTS
Defined by SUSPEND constraint
tAWAKE_GTS
tSUSPEND_DISABLE
Blocked
tSUSPEND_ENABLE
Figure 10: Suspend Mode Timing
DS610-3_08_061207
Table 44: Suspend Mode Timing Parameters
Symbol
Description
Min Typ Max Units
Entering Suspend Mode
TSUSPENDHIGH_AWAKE Rising edge of SUSPEND pin to falling edge of AWAKE pin without glitch filter â
7
â ns
(suspend_filter:No)
TSUSPENDFILTER
Adjustment to SUSPEND pin rising edge parameters when glitch filter
enabled (suspend_filter:Yes)
+160 +300 +600 ns
TSUSPEND_GTS
Rising edge of SUSPEND pin until FPGA output pins drive their defined
SUSPEND constraint behavior
â
10
â ns
TSUSPEND_GWE
Rising edge of SUSPEND pin to write-protect lock on all writable clocked
â
<5
â ns
elements
TSUSPEND_DISABLE
Rising edge of the SUSPEND pin to FPGA input pins and interconnect
disabled
â
340
â ns
Exiting Suspend Mode
TSUSPENDLOW_AWAKE Falling edge of the SUSPEND pin to rising edge of the AWAKE pin. Does not â 4 to 108 â
µs
include DCM lock time.
TSUSPEND_ENABLE
Falling edge of the SUSPEND pin to FPGA input pins and interconnect
re-enabled
â 3.7 to 109 â µs
TAWAKE_GWE1
Rising edge of the AWAKE pin until write-protect lock released on all writable â
67
â ns
clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:1.
TAWAKE_GWE512
Rising edge of the AWAKE pin until write-protect lock released on all writable â
14
â µs
clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:512.
TAWAKE_GTS1
Rising edge of the AWAKE pin until outputs return to the behavior described â
57
â ns
in the FPGA application, using sw_clk:InternalClock and sw_gts_cycle:1.
TAWAKE_GTS512
Rising edge of the AWAKE pin until outputs return to the behavior described â
14
â µs
in the FPGA application, using sw_clk:InternalClock and
sw_gts_cycle:512.
Notes:
1. These parameters based on characterization.
2. For information on using the Spartan-3A Suspend feature, see XAPP480: Using Suspend Mode in Spartan-3 Generation FPGAs.
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
53
|
▷ |