XC3S50A-4FTG256C Datasheet, PDF (50/132 Pages) Xilinx, Inc – Architectural and Configuration Overview

DC and Switching Characteristics
Table 39: Switching Characteristics for the DFS(Continued)
Symbol
Lock Time
LOCK_FX^{(2, 3)}
Description
Device
Speed Grade
-5
-4
Min
Max
Min
Max
Units
The time from deassertion at the DCM’s
Reset input to the rising transition at its
5 MHz < F_CLKIN All
< 15 MHz
–
5
–
5
ms
LOCKED output. The DFS asserts
LOCKED when the CLKFX and CLKFX180
signals are valid. If using both the DLL and
F_CLKIN >
15 MHz
450
450
µs
–
–
the DFS, use the longer locking time.
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8 and Table 38.
2. DFS performance requires the additional logic automatically added by ISE 9.1i and later software revisions.
3. For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
4. Maximum output jitter is characterized within a reasonable noise environment (150 ps input period jitter, 40 SSOs and 25% CLB switching)
on an XC3S1400A FPGA. Output jitter strongly depends on the environment, including the number of SSOs, the output drive strength, CLB
utilization, CLB switching activities, switching frequency, power supply and PCB design. The actual maximum output jitter depends on the
system application.
5. The CLKFX and CLKFX180 outputs always have an approximate 50% duty cycle.
6. Some duty-cycle and alignment specifications include a percentage of the CLKFX output period. For example, the data sheet specifies a
maximum CLKFX jitter of “±[1% of CLKFX period + 200]”. Assume the CLKFX output frequency is 100 MHz. The equivalent CLKFX period
is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 200 ps] = ±300 ps.
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DS529-3 (v2.0) August 19, 2010