XC3S50A-4FTG256C Datasheet, PDF (79/132 Pages) Xilinx, Inc – Architectural and Configuration Overview

Pinout Descriptions
FT256: 256-ball Fine-pitch, Thin Ball Grid Array
The 256-ball fine-pitch, thin ball grid array package, FT256,
supports all five Spartan-3A FPGAs. The XC3S200A and
XC3S400A have identical footprints, and the XC3S700A
and XC3S1400A have identical footprints. The XC3S50A is
compatible with the XC3S200A/XC3S400A but has 51
unconnected balls. The XC3S200A/XC3S400A is similar to
the XC3S700A/XC3S1400A, but the XC3S700A/
XC3S1400A adds more power and ground pins and
therefore is not compatible.
Table 68 lists all the package pins for the XC3S50A,
XC3S200A, and XC3S400A. They are sorted by bank
number and then by pin name of the largest device. Pins
that form a differential I/O pair appear together in the table.
The table also shows the pin number for each pin and the
pin type, as defined earlier.
The highlighted rows indicate pinout differences between
the XC3S50A, the XC3S200A, and the XC3S400A FPGAs.
The XC3S50A has 51 unconnected balls, indicated as N.C.
(No Connection) in Table 68 and Figure 20 and with the
black diamond character (‹) in Table 68. Figure 21
provides the common footprint for the XC3S200A and
XC3S400A.
Table 68 also indicates that some differential I/O pairs have
different assignments between the XC3S50A and the
XC3S200A/XC3S400A, highlighted in light blue. See
"Footprint Migration Differences," page 99 for additional
information.
All other balls have nearly identical functionality on all three
devices. Table 73 summarizes the XC3S50A FPGA footprint
migration differences for the FT256 package.
The XC3S50A does not support the address output pins for
the Byte-wide Peripheral Interface (BPI) configuration mode.
Table 69 lists all the package pins for the XC3S700A and
XC3S1400A. They are sorted by bank number and then by
pin name. Pins that form a differential I/O pair appear
together in the table. The table also shows the pin number
for each pin and the pin type, as defined earlier. Figure 22
provides the common footprint for the XC3S200A and
XC3S400A.
An electronic version of this package pinout table and
footprint diagram is available for download from the Xilinx
website at
www.xilinx.com/support/documentation/data_sheets/
s3a_pin.zip.
Pinout Table
Table 68: Spartan-3A FT256 Pinout (XC3S50A,
XC3S200A, XC3S400)
Bank
XC3S50A
XC3S200A FT256
XC3S400A Ball
0 IO_L01N_0
IO_L01N_0
C13
0 IO_L01P_0
IO_L01P_0
D13
0 IO_L02N_0
IO_L02N_0
B14
0
IO_L02P_0/
VREF_0
IO_L02P_0/
VREF_0
B15
0 IO_L03N_0
IO_L03N_0
D11
0 IO_L03P_0
IO_L03P_0
C12
0 IO_L04N_0
IO_L04N_0
A13
0 IO_L04P_0
IO_L04P_0
A14
0
N.C. (◆)
IO_L05N_0
A12
0 IP_0
IO_L05P_0
B12
0
N.C. (◆)
IO_L06N_0/
VREF_0
E10
0
N.C. (◆)
IO_L06P_0
D10
0 IO_L07N_0
IO_L07N_0
A11
0 IO_L07P_0
IO_L07P_0
C11
0 IO_L08N_0
IO_L08N_0
A10
0 IO_L08P_0
IO_L08P_0
B10
0
IO_L09N_0/
GCLK5
IO_L09N_0/
GCLK5
D9
0
IO_L09P_0/
GCLK4
IO_L09P_0/
GCLK4
C10
0
IO_L10N_0/
GCLK7
IO_L10N_0/
GCLK7
A9
0
IO_L10P_0/
GCLK6
IO_L10P_0/
GCLK6
C9
0
IO_L11N_0/
GCLK9
IO_L11N_0/
GCLK9
D8
0
IO_L11P_0/
GCLK8
IO_L11P_0/
GCLK8
C8
0
IO_L12N_0/
GCLK11
IO_L12N_0/
GCLK11
B8
0
IO_L12P_0/
GCLK10
IO_L12P_0/
GCLK10
A8
0 N.C. (◆)
IO_L13N_0
C7
0 N.C. (◆)
IO_L13P_0
A7
0 N.C. (◆)
IO_L14N_0/
VREF_0
E7
0 N.C. (◆)
IO_L14P_0
F8
0 IO_L15N_0
IO_L15N_0
B6
0 IO_L15P_0
IO_L15P_0
A6
0 IO_L16N_0
IO_L16N_0
C6
0 IO_L16P_0
IO_L16P_0
D7
0 IO_L17N_0
IO_L17N_0
C5
Type
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
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