XC3S50A-4FTG256C Datasheet, PDF (119/132 Pages) Xilinx, Inc – Architectural and Configuration Overview

Pinout Descriptions
FG676: 676-ball Fine-pitch Ball Grid Array
The 676-ball fine-pitch ball grid array, FG676, supports the
XC3S1400A FPGA.
Table 87 lists all the FG676 package pins. They are sorted
by bank number and then by pin name. Pairs of pins that
form a differential I/O pair appear together in the table. The
table also shows the pin number for each pin and the pin
type, as defined earlier.
The XC3S1400A has 17 unconnected balls, indicated as
N.C. (No Connection) in Table 87 and with the black
diamond character (‹) in Table 87 and Figure 27.
An electronic version of this package pinout table and
footprint diagram is available for download from the Xilinx
website at:
www.xilinx.com/support/documentation/data_sheets/
s3a_pin.zip.
Pinout Table
Table 87: Spartan-3A FG676 Pinout
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pin Name
IO_L01N_0
IO_L01P_0
IO_L02N_0
IO_L02P_0/VREF_0
IO_L05N_0
IO_L05P_0
IO_L06N_0
IO_L06P_0
IO_L07N_0
IO_L07P_0
IO_L08N_0
IO_L08P_0
IO_L09N_0
IO_L09P_0
IO_L10N_0
IO_L10P_0
IO_L11N_0
IO_L11P_0
IO_L12N_0
IO_L12P_0
IO_L13N_0
IO_L13P_0
IO_L14N_0
IO_L14P_0/VREF_0
FG676
Ball
F20
G20
F19
G19
C22
D22
C23
D23
A22
B23
G17
H17
B21
C21
D21
E21
C20
D20
K16
J16
E17
F17
A20
B20
Type
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
Table 87: Spartan-3A FG676 Pinout(Continued)
Bank
Pin Name
FG676
Ball
Type
0
IO_L15N_0
A19
I/O
0
IO_L15P_0
B19
I/O
0
IO_L16N_0
H15
I/O
0
IO_L16P_0
G15
I/O
0
IO_L17N_0
C18
I/O
0
IO_L17P_0
D18
I/O
0
IO_L18N_0
A18
I/O
0
IO_L18P_0
B18
I/O
0
IO_L19N_0
B17
I/O
0
IO_L19P_0
C17
I/O
0
IO_L20N_0/VREF_0
E15 VREF
0
IO_L20P_0
F15
I/O
0
IO_L21N_0
C16
I/O
0
IO_L21P_0
D17
I/O
0
IO_L22N_0
C15
I/O
0
IO_L22P_0
D16
I/O
0
IO_L23N_0
A15
I/O
0
IO_L23P_0
B15
I/O
0
IO_L24N_0
F14
I/O
0
IO_L24P_0
E14
I/O
0
IO_L25N_0/GCLK5
J14 GCLK
0
IO_L25P_0/GCLK4
K14 GCLK
0
IO_L26N_0/GCLK7
A14 GCLK
0
IO_L26P_0/GCLK6
B14 GCLK
0
IO_L27N_0/GCLK9
G13 GCLK
0
IO_L27P_0/GCLK8
F13 GCLK
0
IO_L28N_0/GCLK11
C13 GCLK
0
IO_L28P_0/GCLK10
B13 GCLK
0
IO_L29N_0
B12
I/O
0
IO_L29P_0
A12
I/O
0
IO_L30N_0
C12
I/O
0
IO_L30P_0
D13
I/O
0
IO_L31N_0
F12
I/O
0
IO_L31P_0
E12
I/O
0
IO_L32N_0/VREF_0
D11 VREF
0
IO_L32P_0
C11
I/O
0
IO_L33N_0
B10
I/O
0
IO_L33P_0
A10
I/O
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
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