DS561 Datasheet, PDF (9/29 Pages) Xilinx, Inc – PLBV46 SLAVE SINGLE

PLBV46 SLAVE SINGLE (v1.01a)
The PLBv46 Slave Single core employs VHDL Generics that are defined as unconstrained arrays as the
method for customizing address space decoding. These parameters are called the Address Range Def-
inition (ARD) arrays. There are two of these arrays used for address space definition in the PLBv46
Slave Single core. They can be recognized by the "C_ARD" prefix of the Generic name. The ARD Gener-
ics are:
• C_ARD_ADDR_RANGE_ARRAY
• C_ARD_NUM_CE_ARRAY
One of the big advantages of using unconstrained arrays for address decode space description is that it
allows the User to specify as few or as many unique and non-contiguous PLB Bus address spaces as the
peripheral design needs. The Slave Attachment decoding logic will be optimized to recognize and
respond to only those defined address spaces during active PLB Bus transaction requests.
Since the number of entries in the arrays can grow or shrink based on each User Application, the slave
attachment is designed to analyze the User's entries in the arrays and then automatically add or remove
resources, and interconnections based on the arrays' contents. A special case arises when there is a sin-
gle entry in an unconstrained array. Refer to the section titled "Single Entry in Unconstrained Array
Parameters" on page 27 for hints on entering data for this case.
The ordering of a set of address space entries within the ARD arrays is not important. Each address
space is processed independently from any of the other address space entries. However, once an order-
ing is established in any one of the arrays, that ordering of the entries must be maintained in the
other ARD array. That is, the first two entries in C_ARD_ADRR_RANGE_ARRAY will be associated
with the first CE Number entry in the C_ARD_NUM_CE_ARRAY.
C_ARD_ADDR_RANGE_ARRAY
The actual address range for an address space definition is entered in this array. Each address space is
by definition a contiguous block of addresses as viewed from the host microprocessor's total address-
able space. It's specification requires a pair of entries in this array. The first entry of the pair is the Base
Address (starting address) of the block, the second entry is the High Address (ending address) of the
block. These addresses are byte relative addresses. The array elements are defined as std_logic_vector(0
to 63) in the ipif_pkg.vhd file in Processor Common (proc_common) library. Currently, the biggest
address bus used on the PLB bus is 32 bits. However, 64 bit values have been allocated for future
growth in address bus width.
C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
-- Base address and high address pairs .
(
X"0000_0000_7000_0000", -- user control reg bank base address
X"0000_0000_7000_0007", -- user control reg bank high address
X"0000_0000_7000_0100", -- user status reg bank base address
X"0000_0000_7000_010F" -- user status reg bank high address
;)
In this example, there are two address pairs
entered into the
C_ARD_ADDR_RANGE_ARRAY VHDL
Generic. This corresponds to the two
address spaces being defined by the user .
Each pair is comprised of a starting address
and an ending address . Values are right
justified and are byte address relative .
Figure 2: Address Range Specification Example
The User must follow several rules when assigning values to the address pairs. These rules assure that
the address range will be correctly decoded in the Slave Attachment. First, the User must decide the
DS561 June 22, 2010
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Product Specification