DS561 Datasheet, PDF (5/29 Pages) Xilinx, Inc – PLBV46 SLAVE SINGLE

PLBV46 SLAVE SINGLE (v1.01a)
Table 1: PLBv46 Slave Single Core I/O Signal Description
Signal Name
Interface Signal Type Init Status
Description
Bus2IP_Addr(0:C_SPLB_AWIDTH
- 1)
User IP
O
Address bus indicating the
0
desired address of the
requested read or write
operation.
Bus2IP_Data(0:C_SIPIF_DWIDTH
-1)
User IP
O
Write data bus to the User
IP. Write data is accepted
by the IP during a write
0
operation by assertion of
the IP2Bus_WrAck signal
and the rising edge of the
Bus2IP_Clk.
Bus2IP_RNW
User IP
O
This signal indicates the
sense of a requested
0
operation with the User IP.
High is a read, low is a
write.
Bus2IP_BE(0:(C_SIPIF_DWIDTH/
8)-1)
User IP
O
Byte enable qualifiers for
the requested read or write
0
operation with the User IP.
Bit 0 corresponds to Byte
lane 0, Bit 1 to Byte lane 1,
and so on.
Bus2IP_CS(0:(C_ARD_ADDR_RA
NGE_ARRAY’length/2) - 1)
User IP
O
Active High chip select
bus. Each bit of the bus
corresponds to an address
pair entry in the
0
C_ARD_ADDR_RANGE_
ARRAY. Assertion of a
chip select indicates a
active transaction request
to the chip select’s target
address space.
DS561 June 22, 2010
www.xilinx.com
5
Product Specification