DS561 Datasheet, PDF (8/29 Pages) Xilinx, Inc – PLBV46 SLAVE SINGLE

PLBV46 SLAVE SINGLE (v1.01a)
Table 2: PLBv46 Slave Single Core Design Parameters
Feature/Description Parameter Name
Allowable Values
FPGA Family Type
Xilinx FPGA Family
C_FAMILY
virtex4, virtex5, virtex6,
spartan6, spartan3a,
aspartan3a, spartan3,
aspartan3, spartan3e,
aspartan3e, spartan3adsp,
aspartan3adsp
Note:
1. This Parameter VHDL type is a custom type defined in the ipif_pkg.vhd.
Parameter - Port Dependencies
Allowable Parameter Combinations
Default
Values
virtex4
VHDL
Type
string
Table 3: PLBv46 Slave Single Core Parameter-Port Dependencies
Name
(Generic or Port)
Affects
(Port)
Depends
(Generic)
Relationship Description
Design Parameters
C_ARD_ADDR_RANGE
_ARRAY
Bus2IP_CS
The vector width of Bus2IP_CS is the
number of elements in
C_ARD_ADDR_RANGE_ARRAY/2
C_ARD_NUM_CE_ARR Bus2IP_WrC
AY
E
The vector width of Bus2IP_WrCE is the
number of elements in
C_ARD_NUM_CE_ARRAY
C_ARD_NUM_CE_ARR Bus2IP_RdC
AY
E
The vector width of Bus2IP_WrCE is the
number of elements in
C_ARD_NUM_CE_ARRAY
I/O Signals
Bus2IP_CS
C_ARD_ADDR_RANG
E_ARRAY
The vector width of Bus2IP_CS is the
number of elements in
C_ARD_ADDR_RANGE_ARRAY/2
Bus2IP_WrCE
C_ARD_NUM_CE_AR
RAY
The vector width of Bus2IP_WrCE is the
number of elements in
C_ARD_NUM_CE_ARRAY
Bus2IP_RdCE
C_ARD_NUM_CE_AR
RAY
The vector width of Bus2IP_WrCE is the
number of elements in
C_ARD_NUM_CE_ARRAY
Parameter Detailed Descriptions
Address Range Definition Arrays
One of the primary functions of the PLBV46 Slave Single is to provide address decoding and Chip
Enable/Chip Select control signal generation.
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DS561 June 22, 2010
Product Specification