DS561 Datasheet, PDF (29/29 Pages) Xilinx, Inc – PLBV46 SLAVE SINGLE

PLBV46 SLAVE SINGLE (v1.01a)
Reference Documents
The following documents contain reference information important to understanding the PLBSlave
Attachment design.
• IBM CoreConnect128-Bit Processor Local Bus, Architectural Specification (v4.6).
Revision History
Date
5/14/08
9/17/08
10/3/08
6/22/10
Version
1.0
1.1
1.2
1.3
Revision
Initial Xilinx release.
Updated resource utilization and performance numbers
Added clarity to the IP2Bus_RdAck and IP2Bus_WrAck signal descriptions to
emphasize that these signals must only be asserted for 1 Bus2IP_Clk cycle.
Added Spartan-6 and Virtex-6 to supported family listing.
DS561 June 22, 2010
www.xilinx.com
29
Product Specification