DS561 Datasheet, PDF (11/29 Pages) Xilinx, Inc – PLBV46 SLAVE SINGLE

PLBV46 SLAVE SINGLE (v1.01a)
clock. For situations where the User IP does not need to run at the bus frequency a dual clock system
can be established where the User IP can run at 1/2 the PLB clock’s frequency. This can improve fmax
for the system. To configure the PLBv46 Slave Single core for this mode of operation set
C_BUS2CORE_CLK_RATIO = 2 for a clock ratio of 2:1. In other words the PLB Bus clock is running a
2X the User IP’s core clock.
NOTE: For proper operation the PLB Clock and the Core Clock must be edge synchronous. This can
be achieved by driving the PLB Clock and the Core Clock from a DCM.
C_SPLB_MID_WIDTH
This parameter is defined as an integer and has a minimum value of 1. It is equal to log₂ of the number
of PLB Masters connected to the PLB bus or 1, whichever is greater. It is used to size the PLB_masterID
bus input from the PLB Bus to the Slave Attachment. For example, if eight PLB Masters are connected
to the PLB Bus, then this parameter must be set to log₂(8) which is equal to 3. The PLB Bus
PLB_masterID bus will be sized to 3 bits wide. If only one master exists, then the parameter needs to be
set to 1. Also, when C_SPLB_P2P = 1 set C_SPLB_MID_WIDTH = 1.
C_SPLB_NUM_MASTERS
This parameter is defined as an integer and is equal to the number of Masters connected to the PLB bus.
This parameter is used to size the Sl_MBusy and Sl_MErr slave reply buses to the PLB. For example, if
eight PLB Masters are connected to the PLB Bus, then this parameter must be set to 8. The Sl_MBusy
bus and Sl_MErr bus will be sized to 8 bits wide each. Also, when C_SPLB_P2P = 1 set
C_SPLB_NUM_MASTERS = 1.
C_SPLB_AWIDTH
This integer parameter is used by the PLB Slave to size the PLB address related components within the
Slave Attachment. This value should be set 32.
C_SPLB_DWIDTH
This integer parameter is used by the PLB Slave to size PLB data bus related components within the
Slave Attachment. This value should be set to match the actual width of the PLB bus, 32, 64 or 128-Bits.
C_SIPIF_DWIDTH
This integer parameter is used to specify the data width of the slave attachment. This parameter is used
to interface various width Slave devices with various width PLB Buses. This value is the native width
of the slave device and is fixed at 32 for this version of slave attachment.
C_INCLUDE_DPHASE_TIMER
This integer value determines whether or not the data phase timeout timer is included. Setting this
value to a 1 will include the data phase timeout timer and setting this value to a 0 will exclude the data
phase timeout timer.
C_FAMILY
This parameter is defined as a string. It specifies the target FPGA technology for implementation of the
PLB Slave. This parameter is required for proper selection of FPGA primitives. The configuration of
these primitives can vary from one FPGA technology family to another.
DS561 June 22, 2010
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11
Product Specification