DS561 Datasheet, PDF (17/29 Pages) Xilinx, Inc – PLBV46 SLAVE SINGLE

PLBV46 SLAVE SINGLE (v1.01a)
Single Beat Read Point-to-Point Operation (C_SPLB_P2P = 1)
In a point-to-point configuration, the cycle can be acknowledge on the same clock cycle as it is
presented. This is shown in Figure 7, where Sl_addrAck goes active in the same cycle as PLB_PAValid.
This reduces latency for read and write cycles.
SPLB_Clk
PLB_masterID[0]
PLB_PAValid
PLB_ABus[0:31]
PLB_size[0:3]
PLB_type[0:2]
PLB_BE[0:3]
PLB_RNW
PLB_wrDBus[0:31]
Sl_wait
Sl_addrAck
Sl_rearbitrate
Sl_MBusy[0]
Sl_wrDack
Sl_wrComp
Sl_rdBus[0:31]
Sl_MRdErr
Sl_rdAck
Sl_rdComp
Bus2IP_Reset
Bus2IP_Clk
Bus2IP_Addr[0:31]
Bus2IP_BE[0:3]
Bus2IP_RNW
Bus2IP_CS[0]
Bus2IP_RdCE[0:15]
Bus2IP_WrCE[0:15]
Bus2IP_Data[0:31]
IP2Bus_WrAck
IP2Bus_Data[0:31]
IP2Bus_RdAck
IP2Bus_Error
50ns
100ns
150ns
200ns
250ns
300ns
350
1
.A0
'b0000
'b000
F
1
.A1
'b0000
'b000
4
1
.D0
1
.D1
.A0
F
1
04000
.D0
.A0
4
1
02000
.D1
Figure 7: PLB Single Data Beat Read Point-to-Point Timing (C_SPLB_P2P = 1)
DS561 June 22, 2010
www.xilinx.com
17
Product Specification