DS561 Datasheet, PDF (19/29 Pages) Xilinx, Inc – PLBV46 SLAVE SINGLE

PLBV46 SLAVE SINGLE (v1.01a)
Single Data Beat Back-to-Back, Point-to-Point Operation (C_SPLB_P2P = 1)
Figure 9 shows two back-to-back read/write cycles from a master in a point-to-point PLB topology.
After the first cycle is acknowledge by the slave attachment (Sl_addrack=’1’), Sl_wait is driven high to
hold off any address phase time-out while the first cycle is being handled by the slave. Upon
completion of the first cycle the second cycle is acknowledge and handled by the slave.
SPLB_Clk
PLB_masterID[0]
PLB_PAValid
PLB_ABus[0:31]
PLB_size[0:3]
PLB_type[0:2]
PLB_BE[0:3]
PLB_RNW
PLB_wrDBus[0:31]
Sl_wait
Sl_addrAck
Sl_rearbitrate
Sl_MBusy[0]
Sl_wrDack
Sl_wrComp
Sl_rdBus[0:31]
Sl_MRdErr
Sl_rdAck
Sl_rdComp
Bus2IP_Reset
Bus2IP_Clk
Bus2IP_Addr[0:31]
Bus2IP_BE[0:3]
Bus2IP_RNW
Bus2IP_CS[0]
Bus2IP_RdCE[0:15]
Bus2IP_WrCE[0:15]
Bus2IP_Data[0:31]
IP2Bus_WrAck
IP2Bus_Data[0]
IP2Bus_RdAck
IP2Bus_Error
50ns
A0
F
100ns
150ns
1
A1
'b0000
'b000
4
D1
1
1
D1
A0
F
1
04000
D0
A1
4
1
02000
D1
200ns
Figure 9: PLB Single Data Beat Back-to-Back, Point-to-Point Read Timing (C_SPLB_P2P = 1)
DS561 June 22, 2010
www.xilinx.com
19
Product Specification