DS561 Datasheet, PDF (10/29 Pages) Xilinx, Inc – PLBV46 SLAVE SINGLE

PLBV46 SLAVE SINGLE (v1.01a)
required address range to be defined. The block size (in bytes) must be a power of 2 (i.e. 2, 4,
8,16,32,64,128,256 and so on). Secondly, the Base Address must start on an address boundary that is a
multiple of the chosen block size. For example, an address space is needed that will include 2048 bytes
(0x800 hex) of the system memory space. Valid Base Address entries are 0x00000000, 0x00000800,
0xFFFFF000, 0x90001000, etc. A value of 0x00000120 is not valid because it is not a multiple of 0x800
(2048). Thirdly, the High Address entry is equal to the assigned Base Address plus the block size minus
1. Continuing the example of a 2048 byte block size, a Base Address of 0x00000000 yields a High
Address of 0x000007FF; a Base Address of 0x00000800 would require a corresponding High Address
value of 0x00000FFF.
C_ARD_NUM_CE_ARRAY
The slave decoding logic provides the User the ability to generate multiple chip enables within a single
address space. This is primarily used to support a bank of registers that need an individual chip enable
for each register. The User enters the desired number of chip enables for an address space in the
C_ARD_NUM_CE_ARRAY. The values entered are positive integers that are powers of 2 (1, 2, 4, 8, 16,
32, and so on). Each address space must have at least 1 chip enable specified. The address space range
will be subdivided and sequentially assigned a chip enable based on a data width or 32 bits.
The User must ensure that the address space for a group of chip enables is greater than or equal to the
specified width of the memory space in bytes (32 / 8 = 4) times the number of desired chip enables.
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE:=
(
4, --User Control Register Bank (4 registers = 4 CEs)
16 --User Status Register Bank (16 registers 16 CEs)
);
In this example, the User defines the number
of CE signals needed per address space .
Figure 3: Chip Enable Specification Example
C_SPLB_P2P
This parameter is defined as an integer. Setting this parameter to 0 will configure the plb_slave_single
for a plb shared bus application. Setting this parameter to 1 will configure the plb_slave_single for a plb
point-to-point bus application. In a point-to-point configuration the slave attachment acknowledges all
address cycles on the plb and only address decodes based on the number CE’s configured for the User
IP. This reduces some FPGA resources. Latency is also reduced in a point-to-point configuration. Note:
If more than 1 address range is defined in C_ARD_ADDR_RANGE_ARRAY in a point-to-point
configuration (i.e. when C_SPLB_P2P = 1) then the slave attachment will instantiate the address
decode logic to distinguish multiple address ranges. This will require a small amount of addition
FPGA resources to be used. For the least amount of required FPGA resources only define 1 address
pair in C_ARD_ADDR_RANGE_ARRAY when C_SPLB_P2P = 1.
C_BUS2CORE_CLK_RATIO
This parameter sets the clock ratio between the PLB Bus clock and the core clock. Setting this parameter
to a 1 will set the ratio to 1:1. Use this setting for cores where the PLB clock is equal to the User IP’s core
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DS561 June 22, 2010
Product Specification