DS561 Datasheet, PDF (7/29 Pages) Xilinx, Inc – PLBV46 SLAVE SINGLE

PLBV46 SLAVE SINGLE (v1.01a)
Design Parameters
The PLBv46 Slave Single core provides for User interface tailoring via VHDL Generic parameters.
These parameters are detailed in Table 2.
The FPGA Family Type parameter is used to select the target FPGA family type. Currently, this design
supports Virtex-4, Virtex-5 and Spartan-3 family of devices.
Table 2: PLBv46 Slave Single Core Design Parameters
Feature/Description Parameter Name
Allowable Values
Default
Values
Decoder Address Range Definition
Array of Base Address / High
Address Pairs for each
Address Range
C_ARD_ADDR_
RANGE_ARRAY
See "Parameter Detailed User must
Descriptions" on page 8 set values.
Array of the desired number
of chip enables for each
address range
C_ARD_NUM_
CE_ARRAY
See "Parameter Detailed User must
Descriptions" on page 8 set values.
PLB I/O Specification
PLB Master ID Bus Width
C_SPLB_MID_
WIDTH
log₂(C_SPLB_NUM_MAST
ERS) with a minimum value
of 1
3
Number of PLB Masters
C_SPLB_NUM_
MASTERS
1 to 16
8
Width of the PLB Least
Significant Address Bus
C_SPLB_AWIDTH 32
32
Width of the PLB Data Bus C_SPLB_DWIDTH 32, 64, 128
32
Selects point-to-point or
shared plb topology.
C_SPLB_P2P
0 = Shared Bus Topology
1 = Point-to-Point Bus
Topology
0
Selects the ratio of bus clock
to core clock for use in dual
clock systems.
C_BUS2CORE_
CLK_RATIO
1 = Ratio of Bus Clock to
Core clock is 1:1
2 = Ratio of Bus Clock to
Core Clock is 2:1
1
Slave Attachment I/O Specification
Width of the Slave Data Bus C_SIPIF_DWIDTH 32
32
Data Phase Timer
configuration
0 = Exclude data phase
C_INCLUDE_
DPHASE_TIMER
timeout timer
1 = Include data phase
1
timeout timer.
VHDL
Type
SLV64_AR
RAY_TYP
E⁽¹⁾
INTEGER
_ARRAY_
TYPE⁽¹⁾
integer
integer
integer
integer
integer
integer
integer
integer
DS561 June 22, 2010
www.xilinx.com
7
Product Specification