DS561 Datasheet, PDF (26/29 Pages) Xilinx, Inc – PLBV46 SLAVE SINGLE

PLBV46 SLAVE SINGLE (v1.01a)
the Slave Attachment latency will be the same as if there was only 1 address pair defined in
C_ARD_ADDR_RANGE_ARRAY, but some of the LUT savings of the Point-To-Point mode will not be
realized.
For this situation the user should set the base address and high address for the services starting at
X"0000_0000_0000_0000". The Users IP should then follow the service address ranges and have a high
address of X"FFFF_FFFF_FFFF_FFFF". (See Figure 14)
C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
-- Base address and high address pairs .
(
X"0000_0000_7000_0000", -- user control reg bank base address
X"0000_0000_7000_0007", -- user control reg bank high address
X"0000_0000_7000_0100", -- user status reg bank base address
X"0000_0000_7000_010F" -- user status reg bank high address
;)
In this example, there are two address pairs
entered into the
C_ARD_ADDR_RANGE_ARRAY VHDL
Generic. This corresponds to the two
address spaces being defined by the user .
Each pair is comprised of a starting address
and an ending address . Values are right
justified and are byte address relative .
Figure 14: C_ARD_ADDR_RANGE_ARRAY for Point-To-Point Configuration
Note that the Slave Attachment will not acknowledge and address if it falls outside of an address
range defined in C_ARD_ADDR_RANGE_ARRAY. For example, if
C_ARD_ADDR_RANGE_ARRAY is defined as in Figure 14 and a master attempts to read or write
to address 0x80 then the Slave attachment will NOT acknowledge the cycle.
Data Phase Timeout
A data phase timeout function has been incorporated into the PLBv46 Slave Single core to provide a
means to complete a PLB request even when the User IP does not respond with an IP2Bus_RdAck or
IP2Bus_WrAck. If C_INCLUDE_DPHASE_TIMER = 1 and after 128 SPLB_Clk cycles, as measured
from the assertion of Sl_AddrAck, the User IP does not respond with either an IP2Bus_RdAck or
IP2Bus_WrAck the PLBv46 Slave Single core will de-assert the User IP cycle request signals, Bus2IP_CS
and Bus2IP_RdCE or Bus2IP_WrCE, and will assert Sl_rdDAck with Sl_rdDBus=zero for a read cycle
or Sl_wrDAck for a write cycle. This will gracefully terminate the cycle. Note that the requesting master
will have no knowledge that the data phase of the PLB request was terminated in this manner.
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DS561 June 22, 2010
Product Specification