DS561 Datasheet, PDF (6/29 Pages) Xilinx, Inc – PLBV46 SLAVE SINGLE

PLBV46 SLAVE SINGLE (v1.01a)
Table 1: PLBv46 Slave Single Core I/O Signal Description
Signal Name
Interface Signal Type Init Status
Description
Bus2IP_RdCE(0: see note 2)
User IP
O
Active high chip enable
bus. Chip enables are
assigned per the User’s
entries in the
C_ARD_NUM_CE_AR
RAY. These chip
enables are asserted
0
only during active read
transaction requests
with the target address
space and in
conjunction with the
corresponding
sub-address within the
space.
Bus2IP_WrCE(0: see note 2)
User IP
O
Active high chip enable
bus. Chip enables are
assigned per the Users
entries in the
C_ARD_NUM_CE_AR
RAY. These chip
enables are asserted
0
only during active write
transaction requests
with the target address
space and in
conjunction with the
corresponding
sub-address within the
space.
Note:
1. This signal’s function and timing is defined in the IBM_® 128-Bit Processor Local Bus Architecture
Specification Version 4.6.
2. The size of the Bus2IP_RdCE and the Bus2IP_WrCE buses is the sum of the integer values entered in the
C_ARD_NUM_CE_ARRAY
6
www.xilinx.com
DS561 June 22, 2010
Product Specification