DS561 Datasheet, PDF (2/29 Pages) Xilinx, Inc – PLBV46 SLAVE SINGLE

PLBV46 SLAVE SINGLE (v1.01a)
Functional Description
The PLBv46 Slave Single core is designed to provide a User with a quick way to implement light weight
interface between the IBM PLB Bus and a User IP core. This slave service allows for multiple User IP’s
to be interfaced to the PLB bus providing address decoding over various address ranges as configured
by the user. Optionally, the PLBv46 Slave Single core can be optimized for a point to point connection
reducing FPGA resources and improving latency. Figure 1shows a block diagram of the PLBv46 Slave
Single core. The port references and groupings are detailed in Table 1.
The base element of the design is the Slave Attachment. This block provides the basic functionality for
slave operation. It implements the protocol and timing translation between the PLB Bus and the IPIC.
Figure Top x-ref 1
PLBV46_SLAVE_SINGLE
User IP
Design
IPIC
SPLB_Clk
SPLB_Rst
PLB Request& Qualifiers
Slave
Attachment
Slave Reply
IP Status Reply
Rd/Wr Qualifiers
CS Bus
Read CE Bus
Write CE Bus
Write Data Bus
Read Data Bus
Figure 1: PLBv46 Slave Single Core Block Diagram
I/O Signals
The PLBv46 Slave Single core signals are listed and described in Table 1.
Table 1: PLBv46 Slave Single Core I/O Signal Description
Signal Name
Interface Signal Type Init Status
Description
PLB Bus Request and Qualifier Signals
SPLB_Clk
PLB Bus
I
PLB main bus clock. See
table note 1.
SPLB_Rst
PLB Bus
I
PLB main bus reset. See
table note 1.
PLB_ABus(0:31)
PLB Bus
I
See table note 1.
PLB_PAValid
PLB Bus
I
See table note 1.
PLB_masterID(0:C_SPLB_MID_W
IDTH-1)
PLB Bus
I
See table note 1.
PLB_RNW
PLB Bus
I
See table note 1.
2
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DS561 June 22, 2010
Product Specification