DS561 Datasheet, PDF (14/29 Pages) Xilinx, Inc – PLBV46 SLAVE SINGLE

PLBV46 SLAVE SINGLE (v1.01a)
IPIC Transaction Timing
The following section shows timing relationships for PLB and Slave Attachment interface signals
during various read and write accesses.
Single Data Beat Read Operation (C_SPLB_P2P = 0)
Two single beat read cycles are shown in Figure 4. The first cycle shows the User IP data
acknowledging (IP2Bus_RdAck = ’1’) the read cycle in the same clock cycle as Bus2IP_CS and
Bus2IP_RdCE are presented. The second read is acknowledged by the User IP 3 clock cycles after the
presentation of Bus2IP_CS and Bus2IP_RdCE. In either case Sl_rdAck and Sl_rdComp will be asserted
in the next clock cycle after IP2Bus_RdAck is asserted by the User IP.
SPLB_Clk
PLB_masterID[0:7]
PLB_PAValid
PLB_ABus[0:31]
PLB_size[0:3]
PLB_type[0:2]
PLB_BE[0:3]
PLB_RNW
PLB_wrDBus[0:31]
Sl_wait
Sl_addrAck
Sl_rearbitrate
Sl_MBusy[0:7]
Sl_wrDack
Sl_wrComp
Sl_rdBus[0:31]
Sl_MRdErr[0:7]
Sl_rdAck
Sl_rdComp
Bus2IP_Reset
Bus2IP_Clk
Bus2IP_Addr[0:31]
Bus2IP_BE[0:3]
Bus2IP_RNW
Bus2IP_CS[0:15]
Bus2IP_RdCE[0:19]
Bus2IP_WrCE[0:19]
Bus2IP_Data[0:31]
IP2Bus_WrAck
IP2Bus_Data[0:31]
IP2Bus_RdAck
IP2Bus_Error
50ns
100ns
150ns
200ns
250ns
300ns
350
02
.A0
'b0000
'b000
F
04
000000A1
'b0000
'b000
4
20
.D0
08
.D1
.A0
F
0100
04000
.D0
.A1
4
0100
02000
.D1
Figure 4: PLB Single Data Beat Read Timing (C_SPLB_P2P = 0)
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DS561 June 22, 2010
Product Specification