DS561 Datasheet, PDF (28/29 Pages) Xilinx, Inc – PLBV46 SLAVE SINGLE

PLBV46 SLAVE SINGLE (v1.01a)
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Table 5: PLBv46 Slave Single Core FPGA Performance and Resource Utilization
Benchmarks
Parameter Values
Device Resources
f_MAX(1)
11
32 1
Slices
37
Slice
Flip-Flops
91
4-input
LUTs
27
f_MAX(1)
167.8 MHz
1 1 32 0
71
173
32
214.8 MHz
1 2 32 0
63
176
34
178.8 MHz
1 4 32 0
57
181
40
173.1 MHz
2 4,4 32 0
83
191
55
178.8 MHz
2 4,4 64 0
70
191
59
183.4 MHz
2 4,4 128 0
88
191
59
177.7 MHz
Notes:
1. Fmax represents the maximum frequency of the PLBV46 Slave Single in a standalone
configuration. The actual maximum frequency will depend on the entire system and
may be greater or less than what is recorded in this table.
Specification Exceptions
The following High Level PLB features are not supported by the plbv46_slave_single Slave function.
• Bus Master
• Split Bus Transactions
• Address Pipelining
• Abort Transactions
• Fixed Burst
• Indeterminate Burst
• Cacheline
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DS561 June 22, 2010
Product Specification