DS561 Datasheet, PDF (13/29 Pages) Xilinx, Inc – PLBV46 SLAVE SINGLE

PLBV46 SLAVE SINGLE (v1.01a)
Note 2: During read cycles if the User IP does not acknowledge the read request within 128
Bus2IP_Clk cycles the slave attachment will timeout, de-assert the request to the User IP (i.e.
de-assert Bus2IP_CS and Bus2ip_RdCE) and complete the read cycle on the PLB by driving
sl_rddack with sl_rddbus equaling all zeros.
IP2Bus_WrAck
IP2Bus_WrAck is the write data acknowledge signal. This signal is used by the User IP to acknowledge
a write cycle and will cause write control signals, Bus2IP_WrCE, and Bus2IP_CS to de-assert.
Note 1: This signal should only be driven when write control signals are asserted. Driving
IP2Bus_WrAck high when write control signals are NOT asserted will cause undefined results.
What this means is that for a single beat transfer the User IP must drive IP2Bus_WrAck for only one
Bus2IP_Clk cycle.
Note 2: During write cycles if the User IP does not acknowledge the write request within 128
Bus2IP_Clk cycles the slave attachment will timeout, de-assert the request to the User IP (i.e.
de-assert Bus2IP_CS and Bus2ip_WrCE) and complete the write cycle on the PLB by driving
sl_wrdack.
IP2Bus_Error
IP2Bus_Error is used by the User IP to indicate and error has occurred. This signal is only sampled with
IP2Bus_WrAck or IP2Bus_RdAck and is ignored all other times. This signal should only be driven
during read or write cycles.
DS561 June 22, 2010
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Product Specification