DS561 Datasheet, PDF (12/29 Pages) Xilinx, Inc – PLBV46 SLAVE SINGLE

PLBV46 SLAVE SINGLE (v1.01a)
IP Interconnect (IPIC) Signal Description
Bus2IP_Addr
Bus2IP_Addr is a 32 Bit vector that drives valid when Bus2IP_CS and Bus2IP_RdCE or Bus2IP_WrCE
drives high.
Bus2IP_Data
Bus2IP_Data is a vector of width C_SIPIF_DWIDTH and drives valid on writes when Bus2IP_WrCE or
Bus2IP_WrReq drive high.
Bus2IP_RNW
Bus2IP_RNW is a signal indicating the type of transfer in progress and is valid when Bus2IP_CS and
Bus2IP_WrCE or Bus2IP_RdCE is asserted. A high on Bus2IP_RNW indicates the transfer request is a
read of the User IP. A low on Bus2IP_RNW indicates the transfer request is a write to the User IP.
Bus2IP_BE
Bus2IP_BE is a vector of width C_SIPIF_DWIDTH/8. This vector indicates which bytes are valid on
Bus2IP_DATA. Bus2IP_BE becomes valid coincident with Bus2IP_CS.
Bus2IP_CS
Bus2IP_CS is a vector of width C_ARD_ADDR_RANGE_ARRAY’length / 2. In other words, for each
address pare defined in C_ARD_ADDR_RANGE_ARRAY there is 1 Bus2IP_CS defined. This signal
asserts at the beginning of a valid cycle on the IPIC. This signal used in conjunction with Bus2IP_RNW
is especially suited for reading and writing to memory type devices.
Bus2IP_RdCE
Bus2IP_RdCE is a vector of a width that is the sum total of the values defined in
C_ARD_NUM_CE_ARRAY. For each address pair defined in C_ARD_ADDR_RANGE_ARRAY a
number of CE’s can be defined in C_ARD_NUM_CE_ARRAY. Bus2IP_RdCE goes high coincident with
Bus2IP_CS for read type transfers and is especially suited for reading registers.
Bus2IP_WrCE
Bus2IP_WrCE is a vector of a width that is the sum total of the values defined in
C_ARD_NUM_CE_ARRAY. For each address pair defined in C_ARD_ADDR_RANGE_ARRAY a
number of CE’s can be defined in C_ARD_NUM_CE_ARRAY. Bus2IP_WrCE goes high when the write
data is valid on Bus2IP_WrCE and is especially suited for writing to registers.
IP2Bus_Data
IP2Bus_Data is a vector of width C_SIPIF_DWIDTH and is the read data bus. Read data should be
valid when IP2Bus_RdAck is asserted by the User IP.
IP2Bus_RdAck
IP2Bus_RdAck is the read data acknowledge signal. This signal is used by the User IP to acknowledge
a read cycle and will cause read control signals, Bus2IP_RdCE, Bus2IP_CS and Bus2IP_RNW to
de-assert.
Note 1: This signal should only be driven when read control signals are asserted. Driving
IP2Bus_RdAck high when read control signals are NOT asserted will cause undefined results. What
this means is that for a single beat transfer the User IP must drive IP2Bus_RdAck for only one
Bus2IP_Clk cycle.
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DS561 June 22, 2010
Product Specification