DS561 Datasheet, PDF (4/29 Pages) Xilinx, Inc – PLBV46 SLAVE SINGLE

PLBV46 SLAVE SINGLE (v1.01a)
Table 1: PLBv46 Slave Single Core I/O Signal Description
Signal Name
Interface Signal Type Init Status
Description
PLB_wrPendPri(0,1)
PLB Bus
I
Unused
PLB_reqPri(0:1)
PLB Bus
I
Unused
Sl_wrBTerm
PLB Bus
O
0
Unused
Sl_rdWdAddr(0:3)
PLB Bus
O
0
Unused
Sl_rdBTerm
PLB Bus
O
0
Unused
Sl_MIRQ(0:C_SPLB_NUM_MAST
ERS-1)
PLB Bus
O
0
Unused
User IP Signals
Bus2IP_Clk
User IP
O
Synchronization clock
0
provided to User IP. This is
the same as SPLB_Clk.
Bus2IP_Reset
User IP
O
Active high reset for use by
0
the User IP. It is a pass
through of the SPLB_Rst
input.
IP2Bus_Data(0:C_SIPIF_DWIDTH
-1)
User IP
I
Input Read Data bus from
the User IP. Data is
qualified with the assertion
of IP2Bus_RdAck signal
and the rising edge of the
Bus2IP_Clk.
IP2Bus_WrAck
User IP
I
Active high Write Data
qualifier. Write data on the
Bus2IP_Data Bus is
deemed accepted by the
User IP at the rising edge
of the Bus2IP_Clk and the
assertion of the
IP2Bus_WrAck for 1 clock
cycle by the User IP.
IP2Bus_RdAck
User IP
I
Active high read data
qualifier. Read data on the
IP2Bus_Data Bus is
deemed valid at the rising
edge of Bus2IP_Clk and
the assertion of the
IP2Bus_RdAck signal for 1
clock cycle by the User IP.
IP2Bus_Error
User IP
I
Active high signal
indicating the User IP has
encountered an error with
the requested operation.
This signal is asserted in
conjunction with
IP2Bus_RdAck or the
IP2Bus_WrAck.
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DS561 June 22, 2010
Product Specification