DS561 Datasheet, PDF (15/29 Pages) Xilinx, Inc – PLBV46 SLAVE SINGLE

PLBV46 SLAVE SINGLE (v1.01a)
Single Data Beat Write Operation (C_SPLB_P2P = 0)
Two single beat write cycles are shown in Figure 5. The first cycle shows the User IP data
acknowledging (IP2Bus_WrAck = ’1’) the write cycle in the same clock cycle as Bus2IP_CS and
Bus2IP_WrCE are presented. The second write is acknowledged by the User IP 3 clock cycles after the
presentation of Bus2IP_CS and Bus2IP_WrCE. In either case Sl_wrAck and Sl_wrComp will be asserted
in the next clock cycle after IP2Bus_WrAck is asserted by the User IP.
SPLB_Clk
PLB_masterID[0:7]
PLB_PAValid
PLB_ABus[0:31]
PLB_size[0:3]
PLB_type[0:2]
PLB_BE[0:3]
PLB_RNW
PLB_wrDBus[0:31]
Sl_wait
Sl_addrAck
Sl_rearbitrate
Sl_MBusy[0:7]
Sl_MWrErr[0:7]
Sl_wrDack
Sl_wrComp
Sl_rdBus[0:31]
Sl_MRdErr[0:7]
Sl_rdAck
Sl_rdComp
Bus2IP_Reset
Bus2IP_Clk
Bus2IP_Addr[0:31]
Bus2IP_BE[0:3]
Bus2IP_RNW
Bus2IP_CS[0:9]
Bus2IP_RdCE[0]
Bus2IP_WrCE[0:15]
Bus2IP_Data[0:31]
IP2Bus_WrAck
IP2Bus_Data[0:31]
IP2Bus_RdAck
IP2Bus_Error
50ns
100ns
150ns
200ns
250ns
300ns
350
02
A0
'b0000
'b000
F
D0
04
A1
'b0000
'b000
4
D1
20
08
A0
F
100
04000
D0
A1
4
100
02000
D1
Figure 5: PLB Single Data Beat Write Timing (C_SPLB_P2P = 0)
DS561 June 22, 2010
www.xilinx.com
15
Product Specification