DS561 Datasheet, PDF (20/29 Pages) Xilinx, Inc – PLBV46 SLAVE SINGLE

PLBV46 SLAVE SINGLE (v1.01a)
Single Data Beat Read Error Operation (C_SPLB_P2P = 0)
Figure 10 shows a read error being generated by the User IP.
SPLB_Clk
PLB_masterID[0:7]
PLB_PAValid
PLB_ABus[0:31]
PLB_size[0:3]
PLB_type[0:2]
PLB_BE[0:3]
PLB_RNW
PLB_wrDBus[0:31]
Sl_wait
Sl_addrAck
Sl_rearbitrate
Sl_MBusy[0:7]
Sl_wrDack
Sl_wrComp
Sl_rdBus[0:31]
Sl_MRdErr[0:7]
Sl_rdAck
Sl_rdComp
Bus2IP_Reset
Bus2IP_Clk
Bus2IP_Addr[0:31]
Bus2IP_BE[0:3]
Bus2IP_RNW
Bus2IP_CS[0:15]
Bus2IP_RdCE[0:19]
Bus2IP_WrCE[0:19]
Bus2IP_Data[0:31]
IP2Bus_WrAck
IP2Bus_Data[0:31]
IP2Bus_RdAck
IP2Bus_Error
50ns
100ns
150ns
200ns
02
.A0
'b0000
'b000
F
250ns
20
.D0
20
.A0
F
0100
04000
.D0
Figure 10: PLB Read Error Timing (C_SPLB_P2P=0)
20
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DS561 June 22, 2010
Product Specification