DS561 Datasheet, PDF (1/29 Pages) Xilinx, Inc – PLBV46 SLAVE SINGLE

DS561 June 22, 2010
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PLBV46 SLAVE SINGLE
(v1.01a)
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Product Specification
Introduction
The PLBv46 Slave Single (v1.01a) device is part of the
Xilinx family of PLB v4.6 compatible products which
provides a singles only bi-directional interface between
a User IP core and the PLB v4.6 bus standard. This
version of the core has been optimized for slave
operation on the version 4.6 PLB Bus. It does not
provide support for DMA and IP Master Services.
Features
• Compatible with Xilinx PLB v4.6 32, 64 and 128-bit
PLB
• Supports access by 32, 64, and 128-Bit Masters
• Supports 32-Bit slave Configuration
• Supports Single Beat read and write data transfers
of byte (8-bit), half-word (16-bit), and word (32-bit)
widths
• Supports Low latency PLB Point-to-Point topology
LogiCORE™ Facts
Core Specifics
Supported Device
Family
Virtex-4®, Virtex-5, Virtex-6,
Spartan®-3E, Spartan-6,
Automotive Spartan-3E,
Spartan-3, Automotive Spartan-3,
Spartan-3A, Automotive
Spartan-3A, Spartan-3A DSP,
Automotive Spartan-3A DSP
Version of core
plbv46_slave_
single
v1.01a
Resources Used
Min
Max
Slices
37
88
LUTs
27
59
FFs
91
191
Block RAMs
None
Provided with Core
Documentation
Product Specification
Design File Formats VHDL
Constraints File
UCF
Verification
VHDL Test bench
Instantiation Template VHDL Wrapper
Reference Designs &
application notes
None
Design Tool Requirements
Xilinx Implementation
Tools
ISE® 9.2 or later
Verification
ModelSim PE 6.3d
Simulation
ModelSim PE 6.3d
Synthesis
XST
Support
Provided by Xilinx, Inc.
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and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application,
or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implemen-
tation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this imple-
mentation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.
DS561 June 22, 2010
www.xilinx.com
1
Product Specification