DS561 Datasheet, PDF (22/29 Pages) Xilinx, Inc – PLBV46 SLAVE SINGLE

PLBV46 SLAVE SINGLE (v1.01a)
User Application Topics
Understanding and Using IPIC Chip Selects and Chip Enables.
Implementing Chip Select (CS) and Chip Enable (CE) signals is a common design task that is needed
within microprocessor based systems to qualify the selection of registers, ports, and memory via an
address decoding function. The PLB Slave Attachment implements a flexible technique for providing
these signals to Users via the ARD parameters. As such, the User must understand the relationship
between the population of the ARD array parameters and the Bus2IP_CS, the Bus2IP_RdCE, and the
Bus2IP_WrCE buses that are available to the User at the IPIC interface with the Slave Attachment. An
example of ARD Array population and the resulting CS and CE bus generation is shown in Figure 12.
The timing characteristics of these signals are shown in the section titled "IPIC Transaction Timing" on
page 14. The signal set to use for User IP functions is up to the User and the design requirements.
Unused CE and CS signals and associated generation logic will be ’trimmed’ during synthesis and PAR
phases of FPGA development.
Chip Select Bus (Bus2IP_CS(0:n)
A single Chip Select signal is assigned to each address space defined by the User in the ARD arrays.
The Chip Select is asserted (active high) whenever a valid access (Read or Write) is requested of the
address space and has been address acknowledged. It remains asserted until the data phase of the
transfer between the Slave Attachment and the addressed target has completed. The User is provided
the Bus2IP_CS port as part of the IPIC signal set The Bus2IP_CS bus has a one to one correlation to the
number and ordering of address pairs in the C_ARD_ADDR_RANGE_ARRAY parameter. For
example, if the C_ARD_ADDR_RANGE_ARRAY has 10 entries in it, the Bus2IP_CS bus will be sized as
0 to 4. Bus2IP_CS(0) will correspond to the first address space, Bus2IP_CS(1) to the second address
space, and so on. The nature of the Chip Select bus requires the User IP to provide any additional
address discrimination within the address space as well as qualification with the Bus2IP_RNW signal.
Read Chip Enable Bus (Bus2IP_RdCE(0:y)
Bus2ip_RdCE is the chip enable bus for read transactions. Each address space defined in the ARD
arrays are allowed to have 1 or more Chip Enables signals assigned to it. Chip Enables are used for
subdividing an address space into smaller spaces that are each less than or equal to the PLB Bus width.
Generally this is useful for selecting registers and ports during read or write transactions. The Slave
Attachment allows the User to do this via parameters entered in the C_ARD_NUM_CE_ARRAY. For
each defined address space, the User enters the number of desired Chip Enable signals to be generated
for each space. Current implementation requires a value of at least 1 for each space. The data width of
the space, set at 32-bits determines the size of the address slice assigned to each CE signal for the
address space. Bus2ip_RdCE asserts if the request transaction is a read.
Write Chip Enable Bus (Bus2IP_WrCE(0:y)
The Bus2IP_WrCE bus is the same size as the Bus2IP_RdCE bus except that the Bus2IP_WrCE signals
are only asserted if the requested transaction is a write.
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DS561 June 22, 2010
Product Specification