DS561 Datasheet, PDF (27/29 Pages) Xilinx, Inc – PLBV46 SLAVE SINGLE

PLBV46 SLAVE SINGLE (v1.01a)
FPGA Design Application Hints
Single Entry in Unconstrained Array Parameters
Synthesis tools sometimes have problems with positional association of VHDL unconstrained arrays
that have only one entry. To avoid this problem, the User should use named association for the single
array entry. This is shown in the following example:
C_ARD_NUM_CE_ARRAY(16); -- VHDL positional association....may cause synthesis type conflict error
for single entry!
C_ARD_NUM_CE_ARRAY(0 => 16); -- VHDL named association....avoids type conflict error for single
entry.
Register Descriptions
The PLBv46 Slave Single core has no internal registers.
Design Implementation
Target Technology
The intended target technology is a Spartan-3, Virtex-4 and Virtex-5 FPGA.
Device Utilization and Performance Benchmarks
Since the PLBv46 Slave Single core is a module that will be used with other design modules in the
FPGA, the utilization and timing numbers reported in this section are just estimates. As the PLBv46
Slave Single core is combined with other pieces of the FPGA design, the utilization of FPGA resources
and timing will vary from the results reported here.
The resource utilization of this version of the PLBv46 Slave Single core is shown in Table 5 for some
example configurations. The Slave Attachment was synthesized using the Xilinx XST tool. The XST
resource utilization report was then used as the source data for the table.
The PLBv46 Slave Single core benchmarks are shown in Table 5 for a xc5vlx220-2-ff1760 FPGA.
DS561 June 22, 2010
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Product Specification