XA3S500E-4PQG208I Datasheet, PDF (4/37 Pages) Xilinx, Inc – Proven advanced 90-nanometer process technology

R
XA Spartan-3E FPGAs support the following differential
standards:
• LVDS
• Bus LVDS
• mini-LVDS
• RSDS
• Differential HSTL (1.8V, Types I and III)
• Differential SSTL (2.5V and 1.8V, Type I)
• 2.5V LVPECL inputs
Table 2: Available User I/Os and Differential (Diff) I/O Pairs
Package
VQG100
CPG132
TQG144
PQG208
Size (mm)
16 x 16
8x8
22 x 22
28 x 28
Device
User Diff User Diff User Diff User Diff
XA3S100E
66
30
83
35 108 40
(7) (2) (11) (2) (28) (4)
-
-
XA3S250E
66
30
92
41 108 40 158 65
(7) (2) (7) (2) (28) (4) (32) (5)
XA3S500E
-
-
92
41
(7) (2)
-
-
158 65
(32) (5)
XA3S1200E
-
-
-
-
-
-
-
-
XA3S1600E
-
-
-
-
-
-
-
-
FTG256
17 x 17
User Diff
-
-
172 68
(40) (8)
190 77
(41) (8)
190 77
(40) (8)
-
-
FGG400
21 x 21
User Diff
-
-
-
-
-
-
304 124
(72) (20)
304 124
(72) (20)
FGG484
23 x 23
User Diff
-
-
-
-
-
-
-
-
376 156
(82) (21)
Notes:
1. All XA Spartan-3E devices provided in the same package are pin-compatible as further described in Module 4: Pinout Descriptions of
DS312.
2. The number shown in bold indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number
of input-only pins.
DS635 (v2.0) September 9, 2009
www.xilinx.com
Product Specification
4