XA3S500E-4PQG208I Datasheet, PDF (21/37 Pages) Xilinx, Inc – Proven advanced 90-nanometer process technology

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Table 21: CLB Distributed RAM Switching Characteristics
Symbol
Description
Clock-to-Output Times
T_SHCKO
Time from the active edge at the CLK input to data appearing on the
distributed RAM output
Setup Times
T_DS
Setup time of data at the BX or BY input before the active transition at the
CLK input of the distributed RAM
T_AS
Setup time of the F/G address inputs before the active transition at the CLK
input of the distributed RAM
T_WS
Setup time of the write enable input before the active transition at the CLK
input of the distributed RAM
Hold Times
T_DH
Hold time of the BX, BY data inputs after the active transition at the CLK
input of the distributed RAM
T_AH, T_WH
Hold time of the F/G address inputs or the write enable input after the active
transition at the CLK input of the distributed RAM
Clock Pulse Width
T_WPH, T_WPL Minimum High or Low pulse width at CLK input
-4
Min Max
-
2.35
0.46
-
0.52
-
0.40
-
0.15
-
0
-
1.01
-
Units
ns
ns
ns
ns
ns
ns
ns
Table 22: CLB Shift Register Switching Characteristics
Symbol
Description
Clock-to-Output Times
T_REG
Time from the active edge at the CLK input to data appearing on the shift
register output
Setup Times
T_SRLDS
Setup time of data at the BX or BY input before the active transition at the
CLK input of the shift register
Hold Times
T_SRLDH
Hold time of the BX or BY data input after the active transition at the CLK
input of the shift register
Clock Pulse Width
T_WPH, T_WPL Minimum High or Low pulse width at CLK input
-4
Min Max
Units
-
4.16 ns
0.46
-
ns
0.16
-
ns
1.01
-
ns
DS635 (v2.0) September 9, 2009
www.xilinx.com
Product Specification
21