XA3S500E-4PQG208I Datasheet, PDF (29/37 Pages) Xilinx, Inc – Proven advanced 90-nanometer process technology

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Configuration and JTAG Timing
Table 33: Power-On Timing and the Beginning of Configuration
Symbol
T_POR(2)
T_PROG
T_PL(2)
T_INIT
T_ICCK(3)
Description
The time from the application of V_CCINT, V_CCAUX, and V_CCO
Bank 2 supply voltage ramps (whichever occurs last) to the
rising transition of the INIT_B pin
The width of the low-going pulse on the PROG_B pin
The time from the rising edge of the PROG_B pin to the
rising transition on the INIT_B pin
Minimum Low pulse width on INIT_B output
The time from the rising edge of the INIT_B pin to the
generation of the configuration clock signal at the CCLK
output pin
Device
XA3S100E
XA3S250E
XA3S500E
XA3S1200E
XA3S1600E
All
XA3S100E
XA3S250E
XA3S500E
XA3S1200E
XA3S1600E
All
All
-4 Speed Grade
Min
Max
-
5
-
5
-
5
-
5
-
7
0.5
-
-
0.5
-
0.5
-
1
-
2
-
2
250
-
0.5
4.0
Units
ms
ms
ms
ms
ms
μs
ms
ms
ms
ms
ms
ns
μs
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 6. This means power must be applied to all V_CCINT, V_CCO,
and V_CCAUX lines.
2. Power-on reset and the clearing of configuration memory occurs during this period.
3. This specification applies only to the Master Serial, SPI, BPI-Up, and BPI-Down modes.
DS635 (v2.0) September 9, 2009
www.xilinx.com
Product Specification
29