XA3S500E-4PQG208I Datasheet, PDF (26/37 Pages) Xilinx, Inc – Proven advanced 90-nanometer process technology

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Table 27: Switching Characteristics for the DLL (Continued)
Symbol
Duty Cycle⁽⁴⁾
CLKOUT_DUTY_CYCLE_DLL
Phase Alignment⁽⁴⁾
CLKIN_CLKFB_PHASE
CLKOUT_PHASE_DLL
Description
Duty cycle variation for the CLK0, CLK90, CLK180,
CLK270, CLK2X, CLK2X180, and CLKDV outputs,
including the BUFGMUX and clock tree duty-cycle
distortion
Phase offset between the CLKIN and CLKFB inputs
Phase offset between DLL outputs CLK0 to CLK2X
(not CLK2X180)
All others
Lock Time
LOCK_DLL⁽³⁾
Delay Lines
DCM_DELAY_STEP
When using the DLL alone: The time
from deassertion at the DCM’s Reset
input to the rising transition at its
LOCKED output. When the DCM is
locked, the CLKIN and CLKFB
signals are in phase
5 MHz < F_CLKIN <
15 MHz
F_CLKIN > 15 MHz
Finest delay resolution
-4 Speed Grade
Min
Max
Units
-
±[1% of
ps
CLKIN period
+ 400]
-
±200
ps
-
±[1% of
ps
CLKIN period
+ 100]
-
±[1% of
ps
CLKIN period
+ 200]
-
5
ms
-
600
μs
20
40
ps
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 6 and Table 26.
2. Indicates the maximum amount of output jitter that the DCM adds to the jitter on the CLKIN input.
3. For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
4. Some jitter and duty-cycle specifications include 1% of input clock period or 0.01 UI. Example: The data sheet specifies a maximum
jitter of “±[1% of CLKIN period + 150]”. Assume the CLKIN frequency is 100 MHz. The equivalent CLKIN period is 10 ns and 1% of
10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 150 ps] = ±250ps.
Digital Frequency Synthesizer
Table 28: Recommended Operating Conditions for the DFS
Symbol
Input Frequency Ranges⁽²⁾
F_CLKIN
CLKIN_FREQ_FX
Input Clock Jitter Tolerance⁽³⁾
CLKIN_CYC_JITT_FX_LF
CLKIN_CYC_JITT_FX_HF
Description
Frequency for the CLKIN input
Cycle-to-cycle jitter at the CLKIN
input, based on CLKFX output
frequency
F_CLKFX < 150 MHz
F_CLKFX > 150 MHz
-4 Speed Grade
Min
Max
Units
0.200
333⁽⁴⁾
MHz
-
±300
ps
-
±150
ps
CLKIN_PER_JITT_FX
Period jitter at the CLKIN input
-
±1
ns
Notes:
1. DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) are used.
2. If both DFS and DLL outputs are used on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in Table 26.
3. CLKIN input jitter beyond these limits may cause the DCM to lose lock.
4. To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming
clock frequency by two as it enters the DCM.
DS635 (v2.0) September 9, 2009
www.xilinx.com
Product Specification
26