XA3S500E-4PQG208I Datasheet, PDF (3/37 Pages) Xilinx, Inc – Proven advanced 90-nanometer process technology

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Notes:
1. The XA3S1200E and XA3S1600E have two additional DCMs on both the left and right sides as
indicated by the dashed lines. The XA3S100E has only one DCM at the top and one at the bottom.
Figure 1: XA Spartan-3E Family Architecture
Configuration
XA Spartan-3E FPGAs are programmed by loading config-
uration data into robust, reprogrammable, static CMOS con-
figuration latches (CCLs) that collectively control all
functional elements and routing resources. The FPGA’s
configuration data is stored externally in a PROM or some
other non-volatile medium, either on or off the board. After
applying power, the configuration data is written to the
FPGA using any of five different modes:
• Serial Peripheral Interface (SPI) from an
industry-standard SPI serial Flash
• Byte Peripheral Interface (BPI) Up or Down from an
industry-standard x8 or x8/x16 parallel NOR Flash
• Slave Serial, typically downloaded from a processor
• Slave Parallel, typically downloaded from a processor
• Boundary Scan (JTAG), typically downloaded from a
processor or system tester.
I/O Capabilities
The XA Spartan-3E FPGA SelectIO interface supports
many popular single-ended and differential standards.
Table 2 shows the number of user I/Os as well as the num-
ber of differential I/O pairs available for each device/pack-
age combination.
XA Spartan-3E FPGAs support the following single-ended
standards:
• 3.3V low-voltage TTL (LVTTL)
• Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V,
1.5V, or 1.2V
• 3V PCI at 33 MHz
• HSTL I and III at 1.8V, commonly used in memory
applications
• SSTL I at 1.8V and 2.5V, commonly used for memory
applications
DS635 (v2.0) September 9, 2009
www.xilinx.com
Product Specification
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