XA3S500E-4PQG208I Datasheet, PDF (14/37 Pages) Xilinx, Inc – Proven advanced 90-nanometer process technology

R
VCCO = 2.5V
1/4th of Bourns
Part Number
CAT16-LV4F12
165Ω
Z0 = 50Ω
1/4th of Bourns
Part Number
CAT16-PT4F4
VCCO = 2.5V
140Ω _{Z0 = 50Ω}
100Ω
165Ω
DS635_05_082807
Figure 5: External Termination Resistors for BLVDS Transmitter and BLVDS Receiver
Switching Characteristics
I/O Timing
Table 13: Pin-to-Pin Clock-to-Output Times for the IOB Output Path
Symbol
Description
Conditions
Device
Clock-to-Output Times
T_ICKOFDCM
When reading from the Output
Flip-Flop (OFF), the time from
the active transition on the
Global Clock pin to data
appearing at the Output pin. The
DCM is used.
T_ICKOF
When reading from OFF, the
time from the active transition on
the Global Clock pin to data
appearing at the Output pin. The
DCM is not used.
LVCMOS25⁽²⁾, 12mA
output drive, Fast slew rate,
with DCM⁽³⁾
LVCMOS25⁽²⁾, 12mA
output drive, Fast slew rate,
without DCM
XA3S100E
XA3S250E
XA3S500E
XA3S1200E
XA3S1600E
XA3S100E
XA3S250E
XA3S500E
XA3S1200E
XA3S1600E
-4 Speed
Grade
Max
Units
2.79
ns
3.45
ns
3.46
ns
3.46
ns
3.45
ns
5.92
ns
5.43
ns
5.51
ns
5.94
ns
6.05
ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 19 and are based on the operating conditions set forth in
Table 6 and Table 9.
2. This clock-to-output time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or a
standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. If the former is true, add the appropriate
Input adjustment from Table 17. If the latter is true, add the appropriate Output adjustment from Table 18.
3. DCM output jitter is included in all measurements.
4. For minimums, use the values reported by the Xilinx timing analyzer.
DS635 (v2.0) September 9, 2009
www.xilinx.com
Product Specification
14