XA3S500E-4PQG208I Datasheet, PDF (22/37 Pages) Xilinx, Inc – Proven advanced 90-nanometer process technology

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Clock Buffer/Multiplexer Switching Characteristics
Table 23: Clock Distribution Switching Characteristics
Description
Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to O-output
delay
Global clock multiplexer (BUFGMUX) select S-input setup to I0 and I1
inputs. Same as BUFGCE enable CE-input
Frequency of signals distributed on global buffers (all sides)
Symbol
T_GIO
T_GSI
F_BUFG
Maximum
-4 Speed Grade
1.46
0.63
311
Units
ns
ns
MHz
18 x 18 Embedded Multiplier Timing
Table 24: 18 x 18 Embedded Multiplier Timing
Symbol
Description
Combinatorial Delay
T_MULT
Combinatorial multiplier propagation delay from the A and B inputs to
the P outputs, assuming 18-bit inputs and a 36-bit product (AREG,
BREG, and PREG registers unused)
Clock-to-Output Times
T_{MSCKP_P}
Clock-to-output delay from the active transition of the CLK input to valid
data appearing on the P outputs when using the PREG register⁽²⁾
T_{MSCKP_A}
T_{MSCKP_B}
Clock-to-output delay from the active transition of the CLK input to valid
data appearing on the P outputs when using either the AREG or BREG
register⁽³⁾
Setup Times
T_{MSDCK_P}
Data setup time at the A or B input before the active transition at the
CLK when using only the PREG output register (AREG, BREG
registers unused)⁽²⁾
T_{MSDCK_A}
Data setup time at the A input before the active transition at the CLK
when using the AREG input register⁽³⁾
T_{MSDCK_B}
Data setup time at the B input before the active transition at the CLK
when using the BREG input register⁽³⁾
Hold Times
T_{MSCKD_P}
Data hold time at the A or B input before the active transition at the CLK
when using only the PREG output register (AREG, BREG registers
unused)⁽²⁾
T_{MSCKD_A}
Data hold time at the A input before the active transition at the CLK
when using the AREG input register⁽³⁾
T_{MSCKD_B}
Data hold time at the B input before the active transition at the CLK
when using the BREG input register⁽³⁾
-4 Speed Grade
Min
Max
-
4.88⁽¹⁾
-
1.10
-
4.97
3.98
-
0.23
-
0.39
-
-0.97
0.04
0.05
Units
ns
ns
ns
ns
ns
ns
DS635 (v2.0) September 9, 2009
www.xilinx.com
Product Specification
22