XA3S500E-4PQG208I Datasheet, PDF (15/37 Pages) Xilinx, Inc – Proven advanced 90-nanometer process technology

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Table 14: Pin-to-Pin Setup and Hold Times for the IOB Input Path (System Synchronous)
Symbol
Description
Setup Times
T_PSDCM
When writing to the Input Flip-Flop
(IFF), the time from the setup of
data at the Input pin to the active
transition at a Global Clock pin.
The DCM is used. No Input Delay
is programmed.
Conditions
LVCMOS25⁽²⁾,
IFD_DELAY_VALUE = 0,
with DCM⁽⁴⁾
T_PSFD
When writing to IFF, the time from
the setup of data at the Input pin to
an active transition at the Global
Clock pin. The DCM is not used.
The Input Delay is programmed.
LVCMOS25⁽²⁾,
IFD_DELAY_VALUE =
default software setting
Hold Times
T_PHDCM
When writing to IFF, the time from
the active transition at the Global
Clock pin to the point when data
must be held at the Input pin. The
DCM is used. No Input Delay is
programmed.
LVCMOS25⁽³⁾,
IFD_DELAY_VALUE = 0,
with DCM⁽⁴⁾
T_PHFD
When writing to IFF, the time from
the active transition at the Global
Clock pin to the point when data
must be held at the Input pin. The
DCM is not used. The Input Delay
is programmed.
LVCMOS25⁽³⁾,
IFD_DELAY_VALUE =
default software setting
IFD_
DELAY_
VALUE=
Device
0
XA3S100E
XA3S250E
XA3S500E
XA3S1200E
XA3S1600E
2
XA3S100E
3
XA3S250E
2
XA3S500E
5
XA3S1200E
4
XA3S1600E
0
XA3S100E
XA3S250E
XA3S500E
XA3S1200E
XA3S1600E
2
XA3S100E
3
XA3S250E
2
XA3S500E
5
XA3S1200E
4
XA3S1600E
-4 Speed
Grade
Min
Units
2.98
ns
2.59
ns
2.59
ns
2.58
ns
2.59
ns
3.58
ns
3.91
ns
4.02
ns
5.52
ns
4.46
ns
–0.52
ns
0.14
ns
0.14
ns
0.15
ns
0.14
ns
–0.24
ns
–0.32
ns
–0.49
ns
–0.63
ns
–0.39
ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 19 and are based on the operating conditions set forth in
Table 6 and Table 9.
2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from Table 17. If this is true of the data Input, add the
appropriate Input adjustment from the same table.
3. This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from Table 17. If this is true of the data Input, subtract
the appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock’s
active edge.
4. DCM output jitter is included in all measurements.
DS635 (v2.0) September 9, 2009
www.xilinx.com
Product Specification
15