XA3S500E-4PQG208I Datasheet, PDF (30/37 Pages) Xilinx, Inc – Proven advanced 90-nanometer process technology

R
Configuration Clock (CCLK) Characteristics
Table 34: Master Mode CCLK Output Period by ConfigRate Option Setting
Symbol
Description
ConfigRate
Setting
Temperature
Range
T_CCLK1
CCLK clock period by
ConfigRate setting
1
(power-on value
and default value)
I-Grade
Q-Grade
T_CCLK3
3
I-Grade
Q-Grade
T_CCLK6
6
I-Grade
Q-Grade
T_CCLK12
12
I-Grade
Q-Grade
T_CCLK25
25
I-Grade
Q-Grade
T_CCLK50
50
I-Grade
Q-Grade
Minimum
485
242
121
60.6
30.3
15.1
Maximum Units
1,250
ns
625
ns
313
ns
157
ns
78.2
ns
39.1
ns
Notes:
1. Set the ConfigRate option value when generating a configuration bitstream. See Bitstream Generator (BitGen) Options in DS312, Module 2.
Table 35: Master Mode CCLK Output Frequency by ConfigRate Option Setting
Symbol
Description
ConfigRate
Setting
Temperature
Range
Minimum
F_CCLK1
Equivalent CCLK clock
frequency by ConfigRate
setting
1
(power-on value
and default value)
I-Grade
Q-Grade
0.8
F_CCLK3
3
I-Grade
Q-Grade
1.6
F_CCLK6
6
I-Grade
Q-Grade
3.2
F_CCLK12
12
I-Grade
Q-Grade
6.4
F_CCLK25
25
I-Grade
Q-Grade
12.8
F_CCLK50
50
I-Grade
Q-Grade
25.6
Maximum Units
2.1
MHz
4.2
MHz
8.3
MHz
16.5
MHz
33.0
MHz
66.0
MHz
Table 36: Master Mode CCLK Output Minimum Low and High Time
Symbol
Description
ConfigRate Setting
1
3
6
12
25
T_MCCL,
T_MCCH
Master mode CCLK minimum
Low and High time
I-Grade
Q-Grade
235 117 58 29.3 14.5
Units
50
7.3
ns
Table 37: Slave Mode CCLK Input Low and High Time
Symbol
Description
T_SCCL,
T_SCCH
CCLK Low and High time
Min
Max
Units
5
∞
ns
DS635 (v2.0) September 9, 2009
www.xilinx.com
Product Specification
30