XA3S500E-4PQG208I Datasheet, PDF (31/37 Pages) Xilinx, Inc – Proven advanced 90-nanometer process technology

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Master Serial and Slave Serial Mode Timing
Table 38: Timing for the Master Serial and Slave Serial Configuration Modes
Symbol
Description
Clock-to-Output Times
T_CCO
The time from the falling transition on the CCLK pin to data
appearing at the DOUT pin
Setup Times
T_DCC
The time from the setup of data at the DIN pin to the active edge of
the CCLK pin
Hold Times
T_CCD
The time from the active edge of the CCLK pin to the point when
data is last held at the DIN pin
Clock Timing
T_CCH
High pulse width at the CCLK input pin
T_CCL
Low pulse width at the CCLK input pin
F_CCSER
Frequency of the clock signal at
the CCLK input pin
No bitstream compression
With bitstream compression
Slave/
Master
Both
Both
Both
Master
Slave
Master
Slave
Slave
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 6.
2. For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz.
-4 Speed Grade
Min
Max
Units
1.5
10.0
ns
11.0
-
ns
0
-
ns
See Table 36
See Table 37
See Table 36
See Table 37
0
66⁽²⁾ MHz
0
20
MHz
DS635 (v2.0) September 9, 2009
www.xilinx.com
Product Specification
31