XA3S500E-4PQG208I Datasheet, PDF (33/37 Pages) Xilinx, Inc – Proven advanced 90-nanometer process technology

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Serial Peripheral Interface Configuration Timing
Table 40: Timing for SPI Configuration Mode
Symbol
Description
T_CCLK1
T_CCLKn
T_MINIT
Initial CCLK clock period
CCLK clock period after FPGA loads ConfigRate setting
Setup time on VS[2:0] and M[2:0] mode pins before the rising
edge of INIT_B
T_INITM
Hold time on VS[2:0] and M[2:0]mode pins after the rising edge of
INIT_B
T_CCO
T_DCC
T_CCD
MOSI output valid after CCLK edge
Setup time on DIN data input before CCLK edge
Hold time on DIN data input after CCLK edge
Minimum Maximum
(see Table 34)
(see Table 34)
50
-
0
-
See Table 38
See Table 38
See Table 38
Units
ns
ns
Table 41: Configuration Timing Requirements for Attached SPI Serial Flash
Symbol
Description
Requirement
T_CCS
T_DSU
SPI serial Flash PROM chip-select time
SPI serial Flash PROM data input setup time
T_CCS ≤ T_MCCL1 – T_CCO
T_DSU ≤ T_MCCL1 – T_CCO
T_DH
SPI serial Flash PROM data input hold time
T_DH ≤ T_MCCH1
T_V
SPI serial Flash PROM data clock-to-output time
T_V ≤ T_MCCLn – T_DCC
f_C or f_R
Maximum SPI serial Flash PROM clock frequency (also depends
on specific read command used)
f_C ≥
--------------¹----------------
T_CCLKn(min)
Units
ns
ns
ns
ns
MHz
Notes:
1. These requirements are for successful FPGA configuration in SPI mode, where the FPGA provides the CCLK frequency. The post
configuration timing can be different to support the specific needs of the application loaded into the FPGA and the resulting clock source.
2. Subtract additional printed circuit board routing delay as required by the application.
DS635 (v2.0) September 9, 2009
www.xilinx.com
Product Specification
33