XA3S500E-4PQG208I Datasheet, PDF (17/37 Pages) Xilinx, Inc – Proven advanced 90-nanometer process technology

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Table 16: Propagation Times for the IOB Input Path
Symbol
Description
Conditions
IFD_
DELAY_
VALUE
Device
-4 Speed
Grade
Max
Units
Propagation Times
T_IOPLI The time it takes for data to
LVCMOS25⁽²⁾,
0
travel from the Input pin through IFD_DELAY_VALUE = 0
the IFF latch to the I output with
no input delay programmed
All
2.25
ns
T_IOPLID The time it takes for data to
LVCMOS25⁽²⁾,
2
XA3S100E
5.97
ns
travel from the Input pin through IFD_DELAY_VALUE =
the IFF latch to the I output with default software setting
3
XA3S250E
6.33
ns
the input delay programmed
2
XA3S500E
6.49
ns
5
XA3S1200E
8.15
ns
4
XA3S1600E
7.16
ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 19 and are based on the operating conditions set forth in
Table 6 and Table 9.
2. This propagation time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. When this is
true, add the appropriate Input adjustment from Table 17.
Table 17: Input Timing Adjustments by IOSTANDARD
Convert Input Time from
LVCMOS25 to the Following
Signal Standard
(IOSTANDARD)
Add the
Adjustment Below
-4 Speed Grade
Units
Single-Ended Standards
LVTTL
0.43
ns
LVCMOS33
0.43
ns
LVCMOS25
0
ns
LVCMOS18
0.98
ns
LVCMOS15
0.63
ns
LVCMOS12
0.27
ns
PCI33_3
0.42
ns
HSTL_I_18
0.12
ns
HSTL_III_18
0.17
ns
SSTL18_I
0.30
ns
SSTL2_I
0.15
ns
Table 17: Input Timing Adjustments by IOSTANDARD
Convert Input Time from
LVCMOS25 to the Following
Signal Standard
(IOSTANDARD)
Add the
Adjustment Below
-4 Speed Grade
Units
Differential Standards
LVDS_25
0.49
ns
BLVDS_25
0.39
ns
MINI_LVDS_25
0.49
ns
LVPECL_25
0.27
ns
RSDS_25
0.49
ns
DIFF_HSTL_I_18
0.49
ns
DIFF_HSTL_III_18
0.49
ns
DIFF_SSTL18_I
0.30
ns
DIFF_SSTL2_I
0.32
ns
Notes:
1. The numbers in this table are tested using the methodology
presented in Table 19 and are based on the operating conditions
set forth in Table 6, Table 9, and Table 11.
2. These adjustments are used to convert input path times originally
specified for the LVCMOS25 standard to times that correspond to
other signal standards.
DS635 (v2.0) September 9, 2009
www.xilinx.com
Product Specification
17