XA3S500E-4PQG208I Datasheet, PDF (23/37 Pages) Xilinx, Inc – Proven advanced 90-nanometer process technology

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Table 24: 18 x 18 Embedded Multiplier Timing (Continued)
Symbol
Description
Clock Frequency
F_MULT
Internal operating frequency for a two-stage 18x18 multiplier using the
AREG and BREG input registers and the PREG output register⁽¹⁾
-4 Speed Grade
Min
Max
0
240
Notes:
1. Combinatorial delay is less and pipelined performance is higher when multiplying input data with less than 18 bits.
2. The PREG register is typically used in both single-stage and two-stage pipelined multiplier implementations.
3. Input registers AREG or BREG are typically used when inferring a two-stage multiplier.
Block RAM Timing
Table 25: Block RAM Timing
Symbol
Description
Clock-to-Output Times
T_BCKO
When reading from block RAM, the delay from the active transition
at the CLK input to data appearing at the DOUT output
Setup Times
T_BACK
Setup time for the ADDR inputs before the active transition at the
CLK input of the block RAM
T_BDCK
Setup time for data at the DIN inputs before the active transition at
the CLK input of the block RAM
T_BECK
Setup time for the EN input before the active transition at the CLK
input of the block RAM
T_BWCK
Setup time for the WE input before the active transition at the CLK
input of the block RAM
Hold Times
T_BCKA
Hold time on the ADDR inputs after the active transition at the CLK
input
T_BCKD
Hold time on the DIN inputs after the active transition at the CLK
input
T_BCKE
T_BCKW
Hold time on the EN input after the active transition at the CLK input
Hold time on the WE input after the active transition at the CLK input
-4 Speed Grade
Min
Max
-
2.82
0.38
-
0.23
-
0.77
-
1.26
-
0.14
-
0.13
-
0
-
0
-
Units
MHz
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS635 (v2.0) September 9, 2009
www.xilinx.com
Product Specification
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