XA3S500E-4PQG208I Datasheet, PDF (35/37 Pages) Xilinx, Inc – Proven advanced 90-nanometer process technology

R
IEEE 1149.1/1553 JTAG Test Access Port Timing
Table 44: Timing for the JTAG Test Access Port
-4 Speed Grade
Symbol
Description
Min
Max
Clock-to-Output Times
T_TCKTDO
The time from the falling transition on the TCK pin
1.0
11.0
to data appearing at the TDO pin
Setup Times
T_TDITCK
The time from the setup of data at the TDI pin to
7.0
-
the rising transition at the TCK pin
T_TMSTCK
The time from the setup of a logic level at the TMS
7.0
-
pin to the rising transition at the TCK pin
Hold Times
T_TCKTDI
The time from the rising transition at the TCK pin
0
-
to the point when data is last held at the TDI pin
T_TCKTMS
The time from the rising transition at the TCK pin
0
-
to the point when a logic level is last held at the
TMS pin
Clock Timing
T_CCH
T_CCL
F_TCK
The High pulse width at the TCK pin
The Low pulse width at the TCK pin
Frequency of the TCK signal
5
-
5
-
-
25
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 6.
Units
ns
ns
ns
ns
ns
ns
ns
MHz
DS635 (v2.0) September 9, 2009
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Product Specification
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